Korea Cycle Data

  Dario Amodei's call to "pace the frontier" is being read as an AI slowdown story. For anyone following semiconductors, the more consequential line sits halfway down the essay: do not sell powerful AI chips or chipmaking equipment to China. In his framework, chips are not a demand variable to be cut. They are the lever that makes slowing down affordable. KEY TAKEAWAYS 1. The essay, dated September 2026, lays out a three-step plan and states that pacing "does not mean halting model training or technical progress." 2. It argues democracies can only slow down by as much as their lead over China, and that chip and tool restrictions could widen America's lead significantly over the next 3–5 years. 3. That runs against the most recent US move: in January 2026, BIS shifted H200-class China licenses from a presumption of denial to case-by-case review. The essay is a proposal, not policy. The essay's structure, drawn from the original text. Track B is where semi...

  Ciena is not assembly constrained. It is epitaxy constrained, and those two problems clear on completely different timetables. That distinction is what separates a backlog you can model from a backlog you cannot. KEY TAKEAWAYS 1. Ciena's $8.5bn backlog is 1.32 years of its $6.42bn FY26 revenue guide. Grow revenue 30% in FY27 and the queue still runs 1.20 years. 2. LightCounting puts 2026 optical transceiver and hardware demand at $39bn, up 53%, with demand about 30% ahead of supply. The root cause it names is InP epitaxy capacity, gated by backordered MOCVD tools. 3. The corporate response is contractual, not commercial. Ciena has locked key component supply through 2029. NVIDIA put $2bn each into Lumentum and Coherent in March for future capacity access rights. What Ciena reported, and what it said afterwards Fiscal Q3 2026 closed on August 1 and was reported on September 3. Revenue was $1.67bn, up 37% year over year, with GAAP gross margin of 45.4%, adjusted gross margin of 46....

  For roughly fifteen years the most expensive part inside a smartphone was the processor. In the second quarter of 2026 that stopped being true. DRAM passed the SoC, and the consequences are now printed on retail price tags in seven regions. KEY TAKEAWAYS 1. TrendForce puts memory at about 34% of the iPhone Pro 256GB bill of materials in 3Q26, up from roughly 10% a year earlier, with total BOM for that model about 38% above its 2025 predecessor. 2. The pass-through is smaller than the cost increase and unevenly distributed. Retail prices are projected up 10-20% against a 38% BOM increase, and the gap is absorbed in vendor margin. 3. Where the increase lands matters more than its size. Samsung's Galaxy S26 base 256GB rose 99,000 won while the 512GB version rose 209,000 won — the storage tier, not the headline price, carries the memory bill. The 1H27 figure is a TrendForce projection, not a reported number. What the cost data actually says TrendForce's August 10, 2026 release es...

  A 22% smaller die is worth roughly 25% off cost per good die, but only if the wafer price stays put. Push the wafer price up more than 32.6% and the entire area gain disappears. That threshold is the whole argument, and almost no announcement gives you the numbers to locate it. KEY TAKEAWAYS 1. Cutting die area 22% lifts good die per 300mm wafer by 32.6%, not 22%. Edge loss and defect yield both improve alongside the shrink. 2. The break-even is a 32.6% wafer price increase. Above that, cost per good die rises despite the smaller die. 3. Samsung's own published figure for the SF3 to SF2 node step is 5% area. The 22% NPU number circulating this month comes from a trade report with no stated baseline. Why a smaller die pays more than proportionally A 300mm wafer gives you about 70,686 mm² of usable silicon. At 100 mm² per die the arithmetic says 706 dies. Real placement gets about 640, because dies straddling the round edge are scrap. Drop the die to 78 mm² and you get about 831. T...

  The fastest-growing memory consumer in AI inference is not model weights. It is the KV cache, and it scales with context length and concurrency while HBM capacity stays bounded by what fits on the GPU package. The industry answer is tiering. Marvell's recent product disclosures illustrate the architecture well — but they arrived in two separate announcements five months apart, at different stages of readiness. Sorting out which is which turns out to matter more than any single specification. KEY TAKEAWAYS 1. Marvell states a CXL switch reaching up to 48TB of shared memory, and an optical fabric offloading up to 32TB of warm KV cache across up to 50 meters. All figures are company-stated. 2. The "up to 2-3x higher token throughput" claim is a target. Measurement conditions — model, context length, batch size — have not been disclosed. 3. Nothing here is in production. The CXL switch was slated to sample in Q3 2026, the SSD controller in Q4 2026, and no sampling date has ...

  Oracle closed its fiscal Q1 2027 with a $664bn backlog and negative free cash flow in the same quarter. Those two facts are not in tension. They are the front and back of the same business. The reporting around this print has been unusually muddled — on the revenue figure, on whether guidance was raised, and above all on what a remaining performance obligation actually is. This post walks the chain in order: bookings, delivered capacity, recognized revenue, cash. KEY TAKEAWAYS 1. RPO reached $664bn, up $209bn year over year — roughly 7.4x the $90bn full-year revenue guide. Quarterly revenue was $19.345bn. 2. Operating cash flow hit a record $23.1bn, up 184%, but $28.5bn of capex pushed free cash flow to negative $5.4bn. 3. Oracle delivered 850MW of datacenter capacity and more than 300,000 GPUs in the quarter. That physical delivery, not the contract signing, is what converts backlog into revenue. First, three numbers that are being reported inconsistently Before the analysis, so...