Samsung Puts High-NA EUV in DRAM Before Its Own Logic
High-NA EUV buys resolution by giving up area. Raising the numerical aperture from 0.33 to 0.55 requires anamorphic optics, and that halves the field printed on the wafer. Three announcements landed on September 8 around the SPIE BACUS conference, and all three are answers to that one constraint. ASML and TSMC formed an industry initiative to move the photomask from 6 inches to 12. Samsung joined it and committed to High-NA on DRAM by 2028. Intel said it has now run more than a million wafers on the tools.
KEY TAKEAWAYS
1. At 0.55 NA the demagnification is 4x in one direction and 8x in the other. With an unchanged 6-inch reticle, the wafer field drops from 26 x 33 mm (858 mm²) to 26 x 16.5 mm (429 mm²).
2. Splitting a large die across two half-field exposures — stitching — takes an EXE:5200B from 175 to 125 wafers per hour, roughly 29%, on a tool CNBC reports at around $400 million.
3. Per the ASML and TSMC release, the 12-inch mask pilot line is targeted for 2031 and 12-inch High-NA systems for advanced node production by 2033. Until then, 6-inch masks and stitching.
Three announcements, one constraint
ASML and TSMC formed the initiative on September 7, the day before BACUS opened in Monterey. The joint release is specific about dates: a 12-inch mask pilot line by 2031, with 12-inch High-NA systems entering advanced node production by 2033. It lists three benefits — higher fab productivity, lower chipmaking cost, and removing stitching constraints. TSMC separately said it will use High-NA in high-volume manufacturing for advanced nodes starting in 2030, and expects the number of High-NA layers to grow as transistor architectures get more complex.
Samsung said the same day that it is joining the consortium and targeting High-NA on advanced DRAM production by 2028, which would be a first for memory. Per Samsung's statement, Intel and TSMC are already in. Korean reporting says SK hynix is considering it.
Intel Foundry said it has processed more than one million 300 mm wafers on High-NA, counting tool installation and certification, R&D and production together, and that its High-NA layers in 18A match or exceed the layers they replaced. Those tools are patterning some critical layers of Panther Lake today. For context, ASML said in April 2026 that its entire shipped High-NA base had passed 500,000 wafers. Intel's figure is larger, but it counts a different population over a longer window, so I would not read a share estimate out of the pair.
A note on the name
"12-inch photomask" is ASML's own wording, not a press shorthand. But the format Intel showed at SPIE is 6 x 12 inches. The short side stays at 6 inches (152 mm) and only the long side goes to 12 (304 mm). The name invites the reading that the reticle becomes a 12-inch square. It does not, and the reason is in the optics.
Why only one axis
Today's 0.33 NA EUV demagnifies 4x in both directions, so a 152 x 152 mm reticle prints as 26 x 33 mm.
Raising NA to 0.55 makes light strike the reticle at a shallower angle and mask shadowing becomes unmanageable. ASML and Zeiss solved it by raising demagnification to 8x in the affected direction only. Hold the reticle at 6 inches and that axis halves on the wafer, giving 26 x 16.5 mm. Doubling the reticle in that one direction cancels it exactly. That is why 6 x 12 is not square.
The trade is not one-sided. SPIE material puts the 0.33-to-0.55 transition at roughly 2.8x higher feature density, with fewer multi-patterning steps and shorter cycle time.
The bill for stitching
Any die taller than 16.5 mm has to be exposed twice and joined. That costs three things.
Throughput. 175 wafers per hour becomes 125 on an EXE:5200B. A 29% cut in hourly output on a $400 million tool lands directly on the depreciation carried by each wafer.
Floor planning. The design has to be built around the seam from the start, which removes placement freedom.
Overlay. Interconnects and vias crossing the seam have to line up. A small misalignment distorts lines or breaks connections, and the larger the die, the more expensive each failure is.
This is why Intel is the loudest advocate for a larger reticle, and why "removing stitching constraints" sits in the ASML release alongside productivity and cost. Intel put High-NA into logic first, and logic is where the big dies are.
Samsung is putting memory ahead of its own logic
This is the most interesting line in the whole set. Samsung's DRAM target is 2028. Its foundry target is later. In August 2026, ZDNet Korea reported comments from a Samsung technology executive saying the company had wanted High-NA at 2 nm and 1.4 nm but judged that the technology needs more work, and has settled on inserting it at the 1 nm class instead. Samsung's 1 nm node is slated for 2030. Memory goes two years ahead of logic inside the same company, and two years ahead of TSMC.
Die size explains it. A single DRAM die is not tall enough to hit the 16.5 mm limit, so memory never pays the 29% throughput penalty or takes the seam overlay risk that logic does. High-NA is simply an easier insertion in DRAM than in a large SoC.
Which raises the obvious question: if Samsung does not need stitching, why join a consortium about reticle size? Shot count, most likely. Halving the field doubles the number of exposures needed to cover a wafer. A small die avoids stitching but still pays for the extra shots in time per wafer. A 12-inch mask returns the shot count to where it was. Add the 2030 foundry node and Samsung has little reason to sit out the standard.
What changing a standard actually means
Doubling the reticle is not a reticle problem. Blanks and deposition, etch, inspection and metrology, cleaning, pellicles, mask writers and mask handling all have to be rebuilt around the new format, and the scanner itself needs modification or redesign. The ASML release makes a point of noting that mask suppliers and ecosystem partners attended and expressed interest, which tells you this is not a decision one equipment vendor can make alone.
The calendar says the same thing. Pilot line 2031, production 2033 — five and seven years out. Until then High-NA runs on 6-inch masks and stitching. The 12-inch format is a coordinate, not a tradable event.
One inconsistency worth flagging: the same day, Tom's Hardware reported from an ASML roadmap that High-NA systems arriving before and after 2033 are still designed around 6 x 6 reticles and stitching. That reads differently from the 2033 date in the press release. I have used the press release, as the primary document, but the discrepancy is unresolved.
What I actually watch
| Signal | Why it matters |
|---|---|
| SK hynix joining the consortium | Completes the leading-edge four and changes how fast the format can move |
| ASML quarterly EXE bookings and shipments | Today was a commitment. Bookings are the number. Next report is due mid-October |
| Milestones under Samsung's 2028 target | Tool orders and pilot-line move-in are what make a target real |
| Who builds the 2031 pilot line | Which mask maker and which tools go in decides where the value actually lands |
Value chain read-through
| Segment | Names | Effect of a format change |
|---|---|---|
| Lithography | ASML | Sole High-NA supplier. A 12-inch capable scanner is separate development, targeted for 2033 |
| Mask blanks | Hoya, S&S Tech | Korean sell-side estimates Hoya above 70% of EUV blanks. S&S Tech is the only domestic Korean producer and is just entering EUV volume |
| Pellicles | Mitsui Chemicals, FST, S&S Tech | Very few qualified EUV suppliers. A larger membrane means redesigning area and sag |
| Mask inspection | Lasertec, KLA, Zeiss | Stages and optics are dimensioned to the reticle |
| Device makers | Intel (now), Samsung (2028), TSMC (2030), SK hynix (considering) | The gap in insertion timing becomes a gap in process cost and scaling pace |
Risks to this view
- The 12-inch format is not a standard. The initiative was formed this month and the pilot line is a 2031 target. Expressing interest and building a line are different things.
- Samsung's 2028 DRAM date and TSMC's 2030 are company targets. Tool lead times, the cost-benefit at each node, and alternative paths such as 3D DRAM can all move them.
- The 2033 date in the ASML release and the roadmap description reported by Tom's Hardware do not agree. This post follows the press release.
- Korean materials names above are just entering 6-inch EUV supply, and share figures come from sell-side estimates and press reporting, not disclosure. Throughput, field and price figures are tied to specific tool models as publicly reported.
Closing
High-NA EUV gained resolution and lost area, and the industry is using two methods to get it back. Stitching works today and costs 29% of hourly output. A 12-inch mask fixes the cause and takes five years to a pilot line and seven to production.
The three companies are standing in different places because of that. Intel walks the stitching road and lobbies hardest for the bigger reticle. TSMC waits until 2030 for the tool but co-founds the standard. Samsung enters first in 2028, in the one product where stitching never applies. Three strategies for the same machine, disclosed on the same day.
Sources: ASML and TSMC joint press release (Sept 8, 2026); ZDNet Korea (Sept 8, 2026, two articles); Hankyoreh (Sept 8, 2026); Tom's Hardware (Sept 8, 2026); CNBC (Sept 8, 2026); SPIE International Conference on EUV Lithography 2025 abstracts; Hankyung (Sept 8, 2026); TrendForce (Aug 11, 2026); Electronic Times (Jan 12, 2026); Asia Economy (April 6, 2026).
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