CXMT's HBM3 Yield Is 25%. Its DDR5 Yield Is 90%.
A Korean report this week put CXMT's HBM3 8-Hi yield at roughly 30% through the front end, with about 70% of the survivors clearing back-end test. Multiply those and you get 21 good stacks per 100 wafer starts. The same company, on the same 17nm-class node, was reported a month earlier to be running commodity DDR5 above 90%.
That contrast is the story. The lithography gap between China and the leaders has narrowed. The gap in thinning, drilling, stacking and bonding has not.
KEY TAKEAWAYS
1. The reported stage yields are 30% front end and 70% back end. Multiplied, that is 21% final, not the 25% in the article's lead. The 25% figure matches a SemiAnalysis estimate published two months earlier.
2. CXMT's commodity DDR5 on the same G4 node is reported above 90%, against 21-25% for HBM3 8-Hi. The bottleneck is the 3D stack, not the node.
3. TSV counts run around 3,000 per die at CXMT against 8,000 or more for SK hynix HBM3. But HBM3's data interface is fixed at 1,024 bits by JEDEC, so the count gap is a power and redundancy story, not a data-width one.
What was actually reported
Chosun Biz reported on September 9 that CXMT has begun trial production of HBM3 8-Hi, that front-end yield sits near 30%, and that only about 70% of what survives passes final test. The source is an unnamed senior figure at a semiconductor equipment supplier.
The arithmetic in that report does not close. The lead says yield is stuck at 25%. The two stage figures in the body multiply to 21%. The body's own phrasing, that close to 80 of every 100 units fail, also points to 21 rather than 25.
The 25% has a different origin. SemiAnalysis published an estimate in July 2026 of roughly 35% front end, 70% back end and 25% final. The September report appears to carry a lower front-end number while the lead reuses the older final figure.
Four percentage points will not change anyone's model. The provenance matters more than the digit. Neither number is a company disclosure, and CXMT's H1 2026 interim report does not contain the string HBM anywhere in it, a point I verified against the filing text in an earlier post. The yield of a product that does not appear in the filings is being discussed entirely through unnamed sourcing.
Yield is a product, not a sum
Commodity DRAM ends when the wafer is processed, diced and tested. HBM starts a second manufacturing life at that point. The wafer is thinned to tens of microns, thousands of holes are etched and filled with copper, eight dies are aligned and thermally bonded, and the assembled stack is tested again.
Each of those gates multiplies. Thirty percent times seventy percent is twenty-one percent. Even a chain of five gates at 90% each lands at 59%.
This is not only a challenger's problem. At SK AI Summit 2024, an SK hynix executive walked through a 16-Hi example on stage: assume 80% wafer yield, 80% post-stack verification and 98% KGSD, and the final number falls to 46%. That was the market leader describing its own arithmetic in public.
One more rule compounds it. If a single die in the stack is misaligned, if a void forms at a bond interface, or if the stack warps under thermal compression, the entire stack is scrapped. More layers means more places to fail, so a company at 21% on 8-Hi does not automatically improve at 12-Hi.
Same node, different product
Chinese outlets reported in August that CXMT's 17nm-class DDR5 yield had passed 90%, within about two points of Samsung's same-generation product at a reported 92-93%. Nomura put CXMT's DDR5 yield closer to 80% over the same period. Either estimate sits an order of magnitude away from 21-25%.
Two explanations appear in the reporting. HBM core dies are physically larger than commodity parts, so a given defect density kills a larger share of them. And the electrical bins are tighter, so dies from the same wafer can pass a commodity screen and fail an HBM one.
Put together: the fight over linewidth has narrowed, and the fight over screening large dies to tight limits and then thinning and stacking them has barely started. The observation that US equipment controls bite harder on TSV metrology and bonding than on front-end lithography points the same way.
The TSV count is not a bandwidth dial
The Nomad Semi figures cited in the report give roughly 3,000 TSVs per die for CXMT, 5,000 or more for Samsung HBM2 and 8,000 or more for SK hynix HBM3. The article reads the lower count as trading bandwidth for an easier process.
Half of that holds. HBM3's data interface is fixed at 1,024 bits per stack under JEDEC JESD238, arranged as sixteen 64-bit channels. A part that narrows the data path is not HBM3.
So the difference between 3,000 and 8,000 sits outside the data path. Power and ground delivery, redundancy vias that replace failed connections, and test paths make up the rest. Fewer TSVs does not shrink the bus. It weakens power delivery and removes spare capacity, which caps the pin speed the stack can hold. Bandwidth suffers through that route, not directly.
The distinction matters because the remedies differ. A data-width problem is a design change. A power-integrity and redundancy problem requires the TSV etch, plating and thinning process itself to mature. The second takes far longer.
What I actually watch
| Signal | Why it matters | Timing |
|---|---|---|
| A 12-Hi trial production announcement | More layers means more multiplied gates. Watch whether a yield figure is reported alongside it. | Open |
| HBM appearing in a CXMT filing | Moves the number from unnamed sourcing to something checkable. | Next interim or annual report |
| Rate of yield improvement | Samsung went from under 60% to roughly 80% on HBM4 in six months. Whether CXMT bends the same curve is the question. | Rolling |
| Domestic customer adoption volume | Alibaba T-Head and Cambricon have been named as sample recipients. Captive demand can override cost logic. | Rolling |
Value chain read-through
| Process block | What it decides | What to check |
|---|---|---|
| Wafer thinning and carrier bonding | Warpage and breakage on thinned wafers | Whether 12-Hi trials are announced at all |
| TSV etch, plating and polish | Power integrity, redundancy headroom | TSV count per die across generations |
| Stacking and bonding | Stack-level pass rate | Whether the 70% back-end figure moves |
| Stack test (KGSD) | Share shippable to a customer | Customer qualification announcements |
Risks to this view
- The primary source for these yield numbers is one unnamed industry contact. It is not a disclosure and it is not independently checkable.
- Low yield is not the same as failed market entry. Subsidies and captive domestic demand can absorb cost that a merchant supplier could not.
- The Nomad Semi TSV counts span different generations, HBM2 against HBM3. Treat them as directional, not like-for-like.
- The risk runs the other way too. If CXMT's commodity DDR5 yield really is near 90%, that is already a variable in DDR5 supply regardless of what happens in HBM.
Where this leaves the read
The takeaway is not that China is far behind. It is that HBM competitiveness is decided in a specific place, and that place is downstream of the scanner. Linewidth is being caught. The multiplied 3D chain is not, yet. How fast that chain closes sets the next several years.
Next post: Micron's fiscal Q4 results land late this month, and I will use them to check where memory pricing and shipped volume actually stand.
Sources
Chosun Biz, September 9, 2026 (unnamed equipment-industry source); SemiAnalysis CXMT HBM yield estimate, July 2026, via Newspim; Nomad Semi TSV analysis as cited by Chosun Biz; Chinese media reports on CXMT DDR5 yield, August 2026; Nomura estimate via HK01, August 2026; SK AI Summit 2024 presentation, November 2024, via Bloter; Seoul Economic Daily and Newsway on Samsung HBM4 yield, August 2026; JEDEC JESD238 HBM3 standard summary.
Disclaimer: This post is for informational and educational purposes only. It does not constitute investment advice or a recommendation to buy or sell any security. All investment decisions are your own responsibility.
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