Samsung HBM5 2x, zHBM 8x: Only One Target Has a Date
Samsung used its keynote at the SEMICON Taiwan 2026 Memory Executive Summit on September 1 to put numbers on its next two HBM generations: HBM5 at twice the performance of HBM4E, and a 3D-stacked successor called zHBM at eight times. The headline multiples are large. Two things about them matter more than their size. The "8x" has been quoted against a different baseline in each of Samsung's three talks over the past month, and of the five products on the slide, only one carries a date.
KEY TAKEAWAYS
1. Samsung's stated targets: HBM5 at 2x HBM4E performance, +20% performance per watt, -20% thermal resistance; zHBM at 8x performance, 3x performance per watt, -75% to -90% thermal resistance. All are targets for products described as "in development."
2. The zHBM "8x" was "vs HBM5" at FMS on August 5, "+230% bandwidth vs standard HBM4E" at Hot Chips on August 23, and "vs HBM4E" on September 1. Different metrics and baselines; they cannot be lined up.
3. Only zNAND-O has a date: sampling in 2028. HBM4 (mass production, February) and HBM4E (sampling, May) are done; HBM5 and zHBM have no timeline. SK hynix and SanDisk target HBF samples in 2H 2026.
What Samsung said
The speaker was Choi Jang-seok, vice president and head of memory product planning. "CUBE" stands for capacity, utilization, bandwidth and efficiency, and the framing is that 3D structures, rather than simple vertical stacking, should improve all four at once. The concrete figures, as reported by Korean and English-language outlets working from Samsung's materials:
| Product | Stated target | Baseline | Status | Date |
|---|---|---|---|---|
| HBM4 | 11.7Gbps, 3.3TB/s per stack | - | Mass production | Feb 2026 (done) |
| HBM4E | 16Gbps, 4.0TB/s per stack | - | Sampling, in customer tests | May 2026 (done) |
| HBM5 | 2x performance, +20% perf/W, -20% thermal resistance | HBM4E | In development | None given |
| zHBM | 8x performance, 3x perf/W, -75% to -90% thermal resistance | HBM4E | Concept (mock-up at FMS) | None given |
| zNAND-O | 10x DRAM bit density; 7x NAND read bandwidth and power efficiency | DRAM / NAND | In development, 4- or 8-die TSV stack | Sampling 2028 (target) |
Two reading notes. First, the baseline for zHBM's "8x" is inconsistent across coverage. Most outlets, including The Korea Times, The Korea Herald and ET News, report it as "vs HBM4E." Several Korean outlets report "vs HBM5," which is what Samsung's own newsroom said at FMS 2026 on August 5. This post follows the majority reading for the September 1 talk and flags the split. Second, Samsung did not define "performance." Whether it means per-stack bandwidth, system throughput including capacity, or something else is not specified in the available summaries. The next section checks it against bandwidth figures Samsung has already published.
Three talks, three baselines for the same 8x
zHBM replaces the 2.5D layout, with HBM beside the GPU on an interposer, with memory stacked directly on top of the logic die. Samsung has presented it three times in four weeks:
• August 5, FMS 2026 (Samsung Newsroom): a next-generation interface system incorporating zHBM at roughly 8x the performance of HBM5, more than 10x memory density, 3x energy efficiency, thermal resistance cut by more than half.
• August 23, Hot Chips 2026 (public summaries): +230% bandwidth and +70% power efficiency versus standard HBM4E; about 100W saved in a 1,200W GPU with four zHBM stacks.
• September 1, SEMICON Taiwan: 8x performance, 3x performance per watt, thermal resistance down 75% to 90%, versus HBM4E.
Put side by side these do not reconcile. If HBM5 is 2x HBM4E, as Samsung now targets, then FMS's "8x HBM5" implies 16x HBM4E, while September's figure is 8x. Hot Chips' 3.3x measured bandwidth alone. The right conclusion is not "Samsung cut the number." It is that the metric and the baseline changed each time, so the three figures do not describe the same quantity. What did stay stable across the talks was efficiency: 3x energy efficiency in both August 5 and September 1, and a thermal-resistance target that grew from "more than half" to "75 to 90%." For a design that puts DRAM on top of a logic die drawing over 1,000W, those two numbers are the prerequisite, not the bonus.
HBM5 "2x" is probably not per-stack bandwidth
Samsung has already published per-stack bandwidth for HBM4 (3.3TB/s at 11.7Gbps, 13Gbps peak) and HBM4E (4.0TB/s at 16Gbps). Its Hot Chips slide put HBM5 at 60GB or more and 6TB/s or more. Six divided by four is 1.5. If "2x performance" referred to per-stack bandwidth, the two statements would conflict. More likely it is a system-level figure that folds in capacity (48GB to 60GB+) or stack count per GPU. Read the bandwidth gain as roughly 1.5x until Samsung says otherwise.
There is no JEDEC HBM5 specification yet. The KAIST-TERA roadmap from June 2025 projects HBM5 for 2029 at 4,096 bits wide, 8Gbps per pin, 4TB/s per stack, 16-high, 80GB and 100W per stack. If that holds, HBM5 would repeat what HBM4 did: widen the interface rather than speed up the pins. A 6TB/s stack on 4,096 bits would need roughly 12Gbps per pin. That is arithmetic, not a Samsung statement.
zNAND-O versus HBF: same slot, different clocks
zNAND-O targets the gap between DRAM and NAND. It stacks four or eight NAND dies with TSVs, aiming for 10x the bit density of DRAM and 7x the read bandwidth and power efficiency of conventional NAND, for inference workloads whose KV caches and weights no longer fit in HBM. Sampling is targeted for 2028.
SK hynix and SanDisk are already filling that slot under the name High Bandwidth Flash. On August 4, at FMS 2026, they published the first HBF specification through the Open Compute Project: 8-high and 16-high NAND stacks, up to 512GB, three bandwidth tiers from 0.4 to 3.0TB/s, UCIe to the host, with Google and Tenstorrent in the consortium. Samples are targeted for the second half of 2026 and a first inference system for early 2027.
| Samsung zNAND-O | SK hynix / SanDisk HBF | |
|---|---|---|
| Structure | 4- or 8-die NAND TSV stack | 8- or 16-high NAND stack, up to 512GB |
| Bandwidth | 7x conventional NAND (no absolute figure) | 0.4 to 3.0TB/s, three tiers |
| Standard | None mentioned | Open spec via OCP, UCIe interface |
| Ecosystem | Not disclosed | Google, Tenstorrent |
| Samples | 2028 (target) | 2H 2026 (target) |
Two axes separate them. On time, Samsung's target is about eighteen months later. On standards, HBF is an open spec and zNAND-O is, for now, a single-vendor design. Samsung does hold the largest NAND share (29.3% of Q2 2026 revenue per TrendForce, as reported), so which side that favors is not something the data can settle today.
Announcement, sample and production are different events
Sorted by stage, the keynote contained two achievements and three targets. HBM4 mass production (February) and HBM4E sampling (May, now in customer tests) have happened. HBM5 is "in development" and zHBM is a "concept," neither with a date. zNAND-O has 2028. In order of distance from revenue, HBM4E production qualification is closest; everything else is a 2027-or-later story.
The structural point is direction. zHBM is a DRAM maker putting memory on top of the GPU. Nvidia's NVHBM, covered here last week, is a GPU maker moving the memory controller into the HBM base die. The two companies are walking toward the same boundary between memory and logic from opposite sides. Whoever ends up owning that boundary, the back-end bottlenecks are the same: wafer-to-wafer hybrid bonding, TSVs, heat-path design and customer-specific base dies.
What I actually watch
| When | What | Why |
|---|---|---|
| Sep 2-4 | SEMICON Taiwan main program: SK hynix, Micron sessions | Do competitors attach dates to HBM5 and 3D roadmaps |
| 2H 2026 | Samsung HBM4E qualification; Rubin Ultra HBM4E supplier mix | The only item on the slide that touches 2026 revenue |
| 2H 2026 | SK hynix / SanDisk HBF samples | Whether the 18-month lead over zNAND-O holds |
| Ongoing | JEDEC HBM5 spec timing and I/O width | 4,096 bits would repeat HBM4's "wider not faster" and raise base-die complexity |
| Ongoing | zHBM customer or foundry partnership announcements | Memory-on-GPU cannot become a product without co-design |
Value chain read-through
| Segment | What the keynote implies | Indicator |
|---|---|---|
| Memory makers | Roadmap competition shifting from bandwidth to 3D integration and thermals | HBM4E qualification order; who dates HBM5 first |
| Bonding and TSV equipment | zHBM presumes wafer-to-wafer hybrid bonding | Hybrid bonder orders; the generation where Samsung adopts HCB |
| Thermal materials | -75% to -90% thermal resistance is the precondition for zHBM | Adoption of heat-path structures such as HPB |
| NAND and controllers | HBF vs zNAND-O: open standard vs single-vendor | HBF consortium growth; whether Samsung joins |
| Foundry and base die | As the memory-logic boundary dissolves, base-die design ownership becomes the contest | Base-die foundry sourcing changes |
Risks to this view
• Targets, not specs. 2x and 8x are development goals with no samples and no standard. Three talks with three baselines is itself a sign the figures are still being worked out.
• Heat. Stacking DRAM on a GPU only works if thermal resistance falls to a quarter or less. If that target slips, the performance multiples are moot.
• No standard, customer lock-in. Neither zHBM nor zNAND-O has a public specification. If they proceed as co-designs with one customer, volume is tied to that customer's roadmap.
• Competitor clocks. HBF samples in 2H 2026, zNAND-O in 2028. The gap may decide market structure or may not matter at all.
• Source limits. This post is built from Samsung's newsroom materials and cross-checked press coverage, not the keynote slides themselves. That is also why the baseline is reported differently across outlets.
What an investor should take from the CUBE keynote is not the 8x. It is three things: Samsung has moved the next axis of competition from bandwidth to heat and 3D integration; the targets are early enough that even the baseline is not fixed; and of the five products shown, the only one that touches this year's revenue is HBM4E. Announcements tell you the direction. Dates tell you when the money moves. This one had many directions and one date.
Sources: Coverage of Samsung's SEMICON Taiwan 2026 keynote (The Korea Times, The Korea Herald, ET News, Hankyung and others, Sep 1, 2026); Samsung Global Newsroom, FMS 2026 (Aug 5, 2026) and HBM4 / HBM4E releases (Feb 12 / May 29, 2026); public summaries of Samsung's Hot Chips 2026 talk; SK hynix HBF specification release (Aug 4, 2026); KAIST-TERA HBM roadmap (Jun 2025); JEDEC JESD270-4. Everything here is from public sources.
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