Half of Samsung's 4nm Capacity Now Feeds Its Own Memory Business
Foundry capacity allocation is normally an internal spreadsheet, not a news story. This week it became one. Korean trade press reports that more than half of Samsung's 4nm foundry wafers are now going into HBM4 base dies — chips that feed Samsung's own memory business rather than an external customer.
KEY TAKEAWAYS
1. ZDNet Korea reports over 50% of Samsung's 4nm capacity is allocated to HBM4 base dies. Against an industry estimate of 30,000 wafer starts per month, that implies 15,000 to 18,000 wafers going to a memory product.
2. The demand case sits with Broadcom. Custom AI silicon drove $16.7 billion of AI semiconductor revenue in FY2026 Q3, up 221% year over year, with $21.7 billion guided for Q4.
3. Samsung told investors on its Q2 call that Q3 HBM4 revenue should more than triple sequentially, and that HBM4 will comfortably exceed 60% of total HBM revenue in the second half.
What is confirmed and what is not
This distinction matters more than usual here, because the headline number is not a company disclosure.
Disclosed by Samsung. In February 2026 the company announced it had begun shipping HBM4 in volume, pairing 1c DRAM core dies with a foundry 4nm base die, and quoting 11.7 Gbps — roughly 46% above the 8 Gbps JEDEC standard. On the July 30 earnings call, management guided Q3 HBM4 revenue to more than triple quarter over quarter, with HBM4 comfortably above 60% of total HBM revenue in the second half. Disclosed R&D spending hit 16 trillion won in Q2, up from 11 trillion in Q1 and a quarterly record.
Reported, not disclosed. ZDNet Korea's September 7 story cites a person familiar with the matter putting the HBM4 base die share of 4nm capacity in the 50-60% range, and estimates total 4nm capacity at roughly 30,000 wafers per month across the S5 and S6 lines at Pyeongtaek P2 and P3. Neither figure comes from a filing. That is why the chart above shows both ends of the range rather than a single number.
Sell-side relay. Separately, Korean outlet inews24 summarized a Goldman Sachs note on Samsung's recent non-deal roadshow, which framed HBM4E and HBM5 as the point where customer-specific requirements get complex enough that owning both memory and foundry starts to compound. That is a broker's summary of a private meeting, so treat it accordingly.
The base die stopped being a memory part
An HBM stack is a column of DRAM dies sitting on a base die that manages traffic between those DRAM layers and the accelerator outside. Through HBM3E that base die was built on a memory process. It was a part the DRAM fab made for itself.
HBM4 broke that. The higher bandwidth specification pushed up the signal count and power delivery burden the base die has to carry, past what a memory process handles comfortably. Samsung's answer was to build it on SF4, its 4nm foundry logic node.
The consequence is a capacity coupling that did not exist before. Selling one more HBM stack used to consume DRAM wafers only. It now consumes leading-edge logic wafers too. HBM unit growth translates directly into foundry leading-edge utilization — which is the mechanism behind the reported near-full loading of that node.
Why the demand side justifies the allocation
Broadcom reported FY2026 Q3 on September 2. AI semiconductor revenue reached $16.7 billion, up 221% year over year and 54% sequentially, inside consolidated revenue of $29.6 billion. Q4 AI revenue is guided to $21.7 billion. Management also gave an unusually long-dated outlook: roughly $58 billion of AI revenue in FY2026, about $115 billion in FY2027 and about $230 billion in FY2028. The Wall Street Journal reported that 73% of the quarter's AI revenue came from custom chips.
Custom accelerators change what a memory supplier has to deliver. One standard HBM part no longer covers the market, because bandwidth, power and capacity targets diverge by customer. The base die is where that divergence shows up first — it is the programmable, customer-facing layer of the stack. Samsung and Broadcom signed an agreement in July covering more than $200 billion over five years to 2030, and it spans memory, foundry and advanced packaging together rather than memory alone. The structure of that deal follows the structure of the product.
The synergy has a bill attached
Counterpoint Research puts Q2 2026 HBM revenue share at 50% for SK hynix, 33% for Samsung and 18% for Micron. Samsung gained 12 points from Q1, and the gap to the leader narrowed from 49 points a year earlier to 17. Counterpoint also notes that most HBM revenue still comes from HBM3E, with HBM4 shipments ramping only from the second half. So this scoreboard largely predates the product this post is about.
Owning both sides is genuinely useful. A base die respin does not require a negotiation with an external foundry, and the schedule is yours to set. But the same arrangement carries a cost that does not appear in the synergy story. Every 4nm wafer allocated to an internal memory part is a wafer not available to an external logic customer. Utilization rises; the external customer base does not. For a foundry whose stated problem has been winning outside volume, those are different outcomes.
Samsung is also reported to be continuing its shell-first approach — building fabs and cleanrooms ahead of demand, then installing tools against confirmed orders. That limits overbuild risk. It also means the response to a sudden demand step is bounded by equipment lead times.
What I actually watch
| Signal | Why it matters |
|---|---|
| Q3 HBM4 revenue | The "more than triple" and "above 60%" guidance are forecasts until the quarter prints. |
| Foundry segment result | Higher 4nm loading should show up as a narrower foundry loss. If it does not, the allocation is not paying. |
| External foundry wins | Internal fill improves utilization but not customer diversification. |
| HBM4E timing | Customization pressure genuinely begins at HBM4E, not HBM4. |
Value chain read-through
| Layer | What changes | Metric to track |
|---|---|---|
| HBM core die | 1c DRAM adoption widens | Node mix, bit growth |
| Base die | Consumes leading-edge logic capacity | 4nm loading, foundry margin |
| Advanced packaging | Stacking and bonding difficulty rises | Bonder orders, layer count |
| Customers | Custom accelerators scale | Broadcom quarterly AI revenue and guidance |
Risks to this view
The capacity numbers this post is built on are not disclosed. Both the 30,000 wafer estimate and the 50-60% share come from press reporting and an unnamed source.
Company guidance is guidance. The tripling of HBM4 revenue and Broadcom's FY2028 target are both forecasts, not results.
A larger custom ASIC market does not automatically route volume to any one memory supplier. Qualification decisions still sit with the accelerator designer.
Concentrating leading-edge capacity in one product family is hard to unwind if demand for that family softens.
Closing
Once the base die became a logic chip, the HBM contest stopped being purely about who stacks DRAM best. It became a question of who can move DRAM and leading-edge logic at the same speed. Samsung's 4nm allocation is that question expressed in its most physical form: wafers.
Next post looks at the other side of the same problem — how fast SK hynix is converting its DRAM output to the 1c node.
Sources: ZDNet Korea, September 7, 2026 · inews24, September 7, 2026 · Samsung Newsroom HBM4 mass production release, February 12, 2026 · Samsung Electronics Q2 2026 earnings call, July 30, 2026, and filings · Broadcom FY2026 Q3 results, September 2, 2026, and Q4 guidance · Counterpoint Research Memory Tracker and Forecast Insights Report, Q2 2026 · The Wall Street Journal.
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