2.5D Packaging Explained: Interposers, TSVs, HBM
"Advanced packaging" has become the catch-all phrase for why AI accelerators are supply constrained. Most of the time, the thing being described is 2.5D packaging: a GPU and its HBM stacks placed side by side on a thin silicon layer called an interposer. This post is a primer on how that structure works, why HBM cannot be attached any other way, and why the geometry of the interposer turns directly into a capacity problem.
Everything here is from public sources: TSMC's 3DFabric materials, Yole Group's packaging reports, the JEDEC HBM4 standard, and trade-press capacity estimates. Links are in the Sources line.
KEY TAKEAWAYS
1. 2.5D means dies sit side by side on an interposer that is wired far more densely than a package substrate. Interconnect pitch tightens roughly 10x at each layer: BGA balls at 500-1,000 µm, C4 bumps at 150-200 µm, microbumps at 30-60 µm (40 µm is the HBM norm).
2. The JEDEC HBM4 standard defines a 2,048-bit data interface per stack. Eight stacks means 16,384 data wires that have to fit within a few millimeters of the GPU edge. Organic substrates at ~10 µm line width cannot route that; sub-1 µm interposer wiring can.
3. Because the interposer is itself a wafer-fabricated part, 2.5D is a capacity story. TSMC's CoWoS output is reported to grow from about 13K wafers a month at end-2023 to roughly 170K in 2027, yet larger interposers mean fewer packages per wafer.
Why 2.5D suddenly matters
Yole Group's September 2025 report puts the advanced packaging market at $46 billion in 2024, heading to $79.4 billion by 2030 at a 9.5% CAGR. Mobile and consumer still account for about 70% of revenue, but the fastest segment is telecom and infrastructure at 14.9% a year, driven by AI accelerators, GPUs and chiplet designs. The technologies Yole names for that segment are TSMC CoWoS, Intel EMIB and Samsung I-Cube. All three are 2.5D platforms.
One clarification before the mechanics. HBM itself is a 3D structure: DRAM dies stacked vertically and connected with through-silicon vias. The step that attaches finished HBM stacks next to a GPU is 2.5D. Headlines that lump both under "3D packaging" blur two different supply chains with different bottlenecks.
What the "0.5" stands for
In 2D packaging, several dies sit on an organic package substrate and talk to each other through the substrate's copper traces. This is the multi-chip module, a decades-old approach. In 3D packaging, dies are stacked directly on top of one another and connected vertically with TSVs; HBM's DRAM stack and TSMC's SoIC belong here.
2.5D sits between the two. The dies still lie side by side, but a thin intermediate layer, the interposer, is inserted between them and the substrate. Die-to-die signals run through the interposer rather than the substrate. Nothing is stacked, so it is not 3D; it is not substrate-only either, hence the half step.
The reason for the extra layer is wiring density. ABF organic substrates run at roughly 10 µm line width in volume production, with 2 µm demonstrated in R&D according to IMAPS literature. A silicon interposer is built on a mature front-end process, typically 65 nm class, and its lines drop below 1 µm. Same footprint, tens of times more wires.
Anatomy of a 2.5D package
Reading the stack from the bottom up, there are four connection layers. BGA solder balls join the package to the board. C4 bumps join the substrate to the interposer. Microbumps join the interposer to the dies. And TSVs run vertically through the interposer silicon so that signals and power can reach the substrate.
The division of labor is simple. Horizontal redistribution layers on the interposer surface connect die to die. TSVs connect die to substrate. The interposer is passive in the CoWoS-S case: no transistors, just wiring and vias.
The pitch numbers explain why the layers exist. Public literature puts BGA at 500-1,000 µm, C4 bumps at 150-200 µm and microbumps at 30-60 µm, with 40 µm the common value for HBM attach. Each step up tightens pitch by about 10x, and connection density scales with the square. Going from 150 µm C4 to 40 µm microbumps fits roughly 14x more connections in the same area. (Illustrative calculation. Not actual company figures.)
Those 40 µm bumps are placed with thermocompression bonders. Pushing below 10 µm, or removing bumps entirely with copper hybrid bonding, is the 3D conversation. Today's 2.5D lives at 40 µm.
Why HBM forces the issue: 2,048 wires per stack
HBM gets its bandwidth not by driving each wire faster but by using an enormous number of wires. The JEDEC HBM4 standard published in April 2025 specifies a 2,048-bit data interface per stack, double HBM3E's 1,024 bits.
A GPU with eight HBM4 stacks therefore needs 2,048 x 8 = 16,384 data wires, before command, address and power. All of them must land within a few millimeters of the GPU die edge. At 10 µm line width there is no substrate layer count that makes the area work. At sub-1 µm interposer wiring, the arithmetic closes. (Wire count is a standards-based illustration, not a product specification.)
The corollary matters for demand modeling: chips that do not use HBM do not need 2.5D. GDDR-based accelerators ship on conventional organic substrates. The single upstream variable for 2.5D volume is the number of HBM-equipped dies.
Four flavors of 2.5D
Yole classifies 2.5D by interposer material. Whatever the flavor, the goal is the same: a single die cannot exceed the lithography reticle (about 858 mm²), so the industry connects several dies as densely as possible instead.
| Approach | Interposer | Examples | Trade-off |
|---|---|---|---|
| Silicon interposer | Silicon wafer with TSVs | TSMC CoWoS-S, Samsung I-Cube S, UMC | Densest wiring; size capped near 3.3x reticle (~2,700 mm²) |
| RDL (organic) interposer | Polymer + copper redistribution | TSMC CoWoS-R and InFO, ASE FOCoS, Amkor SWIFT | No TSVs, lower cost; ~2 µm lines |
| Silicon bridge | Small silicon pieces embedded in substrate or mold | Intel EMIB, ASE FOCoS-Bridge, Amkor S-Connect | Silicon only where dense wiring is needed |
| Hybrid (RDL + bridge) | RDL interposer with LSI bridges | TSMC CoWoS-L, Samsung I-Cube E | 5.5x reticle in production, 9x planned for 2027; used by Nvidia Blackwell and Rubin |
A full silicon interposer offers the densest wiring but is itself a chip, so it hits the same reticle wall. TSMC's answer was CoWoS-L: small silicon bridges only under the die edges that need them, RDL everywhere else. TSMC's stated roadmap is 5.5x reticle in 2026 production and 9x in 2027.
This is where cost enters. An interposer consumes an additional wafer pass. Larger interposers improve performance but reduce the number of packages per 300 mm wafer, and the move toward panel-level CoPoS on 310 mm glass panels is fundamentally an attempt to recover that lost area.
The capacity read
Press estimates compiled from TrendForce and Silicon Analysts put TSMC CoWoS at about 13K wafers a month at end-2023, 70K in 2025, 115-140K by end-2026 and about 170K in 2027. TrendForce expects the 2026 supply gap to narrow from 20% to 10% by year-end, and multiple reports say Nvidia has booked more than half of 2026 output, 800-850K wafers. None of this is company-disclosed.
What I actually watch
| Checkpoint | Why it matters |
|---|---|
| HBM-equipped die count | The only upstream variable for 2.5D demand. Includes custom ASICs (TPU, MTIA) adopting HBM, not just GPUs. |
| Scope of CoWoS outsourcing | Whether only the final substrate attach (WoS) or also chip-on-wafer (CoW) goes to ASE, Amkor and SPIL decides how much OSAT revenue follows. |
| Interposer size roadmap | Timing of 9x reticle qualification. Bigger interposers mean fewer packages per wafer, so headline capacity numbers change meaning. |
| TCB bonder orders | 40 µm microbump attach demand comes from both 2.5D and HBM. Watch alongside the pace of hybrid bonder adoption. |
Value chain read-through
| Layer | Companies (examples) | Link to 2.5D |
|---|---|---|
| Interposer fabrication | TSMC, UMC, Samsung | 65 nm class front-end plus TSV. Foundry capacity is packaging capacity. |
| OSAT | ASE/SPIL, Amkor | CoW and WoS outsourcing; own RDL and bridge platforms. |
| Substrates | Ibiden, Shinko, Unimicron, Samsung Electro-Mechanics | Larger interposers need larger ABF substrates, already past 100 x 100 mm. |
| Equipment | BESI, ASMPT, Hanmi Semiconductor, Hanwha Semitech | Thermocompression bonders for microbump attach. |
| Memory | SK hynix, Samsung, Micron | HBM stacks are components placed on the interposer; packaging bottlenecks delay their shipment. |
Risks to this view
- Every capacity figure above is a press or analyst estimate. TSMC's own disclosure is qualitative.
- If Intel EMIB, Samsung I-Cube and OSAT bridge platforms scale, "2.5D equals CoWoS" weakens and TSMC-only tracking undercounts the market.
- A faster shift to hybrid bonding and 3D stacking could shorten the 2.5D equipment cycle. Yole projects hybrid bonder revenue rising from about $152 million in 2025 to $397 million in 2030.
- Company names are given to map the supply chain, not as recommendations.
The whole topic compresses to one sentence: a die cannot get bigger, so several dies are joined as tightly as possible. The interposer is what makes "tightly" possible, and because it is a wafer-made part, it drags capacity and cost along with it. The next post moves one layer up to 3D stacking: TSV-based HBM and hybrid bonding, treated the same way.
Sources: Yole Group, Status of the Advanced Packaging Industry 2025 (press release, Sep 1 2025); Yole Group presentation at SEMI 3D & Systems Summit 2025 (Jun 2025); JEDEC JESD270-4 HBM4 (Apr 2025); TSMC 3DFabric technical materials; TrendForce news (Dec 8 2025; Apr 16 2026; Jun 15 2026); Semiconductor Engineering, "Scaling Bump Pitches in Advanced Packaging" (Dec 2021); IMAPS, "2.5D Interposers and Advanced Organic Substrates Landscape"; HexaMesh (arXiv 2211.13989); Silicon Analysts CoWoS capacity tracker (Mar 2026).
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