2D DRAM's Grace Period: How Far High-NA Pushes Out 3D
How much runway does 2D DRAM have left? Put three public roadmaps on one time axis and a date falls out. ASML's High-NA slide carries single-exposure capacitor scaling to 2033. Samsung's 4F² vertical-channel cell adds density without a lithography shrink from the first sub-10nm generation. Samsung's own target for stacked 3D DRAM is 2030. The three lines converge in 2030-33, and the interesting question is not whether 3D arrives but whether it arrives in shape.
KEY TAKEAWAYS
1. Technically, 2D has runway into the early 2030s: pitch P34 to P22 is worth about 2.4x density, 6F² to 4F² another 1.5x, roughly 3.6x combined against today's 1C.
2. Economically, the curve flattens sooner. Dividing last post's dose-driven throughput model by density gives a lithography cost-per-bit index of 100 at 1C, 48 at 0A and 93 at 0B. The 2D cost curve goes flat in 2030.
3. That is the same year Samsung targets 3D DRAM commercialization. To reach the 200-300 layer cost-parity band by 2032 from a 16-layer demo, 3D DRAM would need about +37% layers per year, faster than 3D NAND's 24% over twelve years.
Three tracks, as publicly stated
| Track | What it does | Public timing | Source |
|---|---|---|---|
| 2D scaling | High-NA single exposure takes capacitor pitch from P34 to P22 | 1C/1D qualified; 0A/0B in qualification; 0C/0D research (2031-33) | ASML roadmap slide, Sep 2026 |
| 4F² VCT | Cell layout 6F² to 4F², about 30% smaller cell at the same lithography node | Samsung: from its first sub-10nm generation. Tokyo Electron: emerging 2027-28 | Samsung Memcon 2024; TEL |
| Stacked 3D DRAM | Cells laid flat and stacked vertically (VS-CAT and similar); density from layer count | Samsung: 16 layers built, commercialize by 2030, stacking beyond 2030. SK hynix: 5-layer test device, 56.1% yield | Samsung IMW 2024; SK hynix VLSI 2024 |
Two distinctions matter. First, 4F² VCT stands the transistor up inside the cell; it does not stack cells. Samsung's roadmap files it under "3D", but from a lithography standpoint it is still 2D scaling. Second, the 200-300 layer cost-parity threshold that gets quoted for 3D DRAM is a SemiEngineering estimate, not a company figure. Public demonstrations today are 5 layers (SK hynix) and 16 (Samsung).
Where 2D density comes from
Bit density per unit area scales with the inverse square of capacitor pitch. P34 to P22 is (34/22)², about 2.4x. Switching the cell from 6F² to 4F² cuts cell area by a third at the same F, another 1.5x. Both together give roughly 3.6x over 1C. Illustrative calculation, cell array only.
This revives an observation from the last post. On the ASML slide, 0B's pitch (P28-30) is no tighter than 0A's P28. Samsung has said it will introduce VCT from its first sub-10nm generation. If pitch pauses and 4F² fills the density gap in that same window, the two documents fit together neatly. Whether the two companies mean the same generation is my connection, not something either has stated.
Lithography cost per bit bottoms at 0A and comes back at 0B
Last post's throughput model (EXE:5200B at 175 WPH and 50 mJ/cm², 40% fixed overhead) gave 135, 147, 189, 106 and 90 WPH for 1C through 0C. Treat the inverse of throughput as the exposure cost of the capacitor layer and the inverse square of pitch as density, and divide. Indexed to 1C = 100, the series runs 71, 48, 93, 95.
The shape is the message. Through 0A, High-NA does what it promises and halves the litho cost per bit. At 0B the dose doubling hands most of that back. The 2D cost curve flattens in 2030, which is exactly Samsung's 3D commercialization target. It is more natural to read the two roadmaps as drawn with an eye on each other than as a coincidence.
3D DRAM has to climb faster than NAND did
3D NAND went from 24 layers in 2013 to 321 in 2025: about 13x in twelve years, a 24% annual pace. For 3D DRAM to go from a 16-layer demo in 2024 to 200 layers by 2032 it needs 12.5x in eight years, roughly 37% a year. Faster than NAND ever sustained.
And DRAM is harder to stack. Every layer needs a capacitor and a current path for refresh, which is why Samsung has said 3D DRAM will require new capacitor and bitline materials. The 37% figure is not anyone's roadmap; it is what the "cost parity by 2032" assumption implies. Miss it and 3D slips past 2033, and 2D's grace period stretches by the same amount.
What a longer grace period does to the cycle
A flat 2D cost curve from 0B plus a late 3D transition is a recipe for structurally slower bit supply growth. TrendForce put server DRAM (RDIMM) bit supply growth at 15-20% a year in July 2026, below server CPU unit growth. When scaling slows, bit growth leans harder on wafer starts, which is to say on capex, and that widens the amplitude of the price cycle rather than dampening it.
The flip side: if High-NA lands cleanly through 0A and 4F² enters production around 2028, the 2028-30 window sees one more large step down in cost per bit. Recall that 0A carried the lowest dose on the ASML slide, 44 mJ/cm². 2028-30 may be the last real cost decline 2D DRAM delivers.
What I actually watch
| Checkpoint | What to look for | When |
|---|---|---|
| 4F² VCT in production | Which of the three DRAM makers first names a 4F² product on a production node, and how it compares with TEL's 2027-28 view | 2027-28 |
| 3D DRAM layer count | Whether the next demo after 16 layers is 32 or 64, and whether it sits above or below the 37% line | IEDM (Dec), VLSI (Jun) |
| 0A qualification | ASML or a customer moving 0A to "process qualified", the precondition for the 2028-30 cost step | 2027-28 |
| Bit supply growth | TrendForce and Counterpoint DRAM bit growth staying in the 15-20% range | Quarterly |
Value chain read-through
| Segment | Direction | Why |
|---|---|---|
| DRAM makers | Supportive for pricing | Flat 2D cost curve plus a late 3D transition lowers structural bit supply growth |
| Lithography tools | Peaks around 2030 | High-NA unit demand concentrates in the 0A-0B insertion; lithography share falls after the 3D transition |
| Etch and deposition | Expands after 2030 | 3D DRAM, like NAND, is bottlenecked by high-aspect-ratio etch and multilayer deposition; a later transition shifts the timing |
| New materials | Long-dated option | 3D capacitor and bitline materials, IGZO channels; Samsung has publicly flagged the need |
Risks to this view
• Both the cost index and the required layer trajectory are illustrative calculations that exclude non-litho process cost, source-power gains and yield.
• The 200-300 layer parity threshold is a third-party estimate. New materials or structures could lower it and pull 3D forward.
• Samsung's "commercialize by 2030" dates from 2024 disclosures; I have not seen an updated official schedule.
• Linking Samsung's 4F² timing to ASML's flat 0B pitch is my reading across two documents, not a stated fact.
Bottom line
"2D DRAM is nearly done" and "High-NA makes 3D a distant problem" are each half right. Laid on one axis, the answer comes out as dates: 2D's grace period runs into the early 2030s, its real cost decline is concentrated in 2028-30, and the window in which 3D must take the baton is 2030-33. Whether 3D DRAM can climb layers faster than NAND ever did inside that window will shape the supply curve of the next cycle.
Next: the source-power race. When does ASML's 1,000W to 1,500W roadmap offset the throughput loss at 128 mJ/cm²? An illustrative calculation.
Sources: ASML High-NA DRAM roadmap slide (September 2026); Samsung Memcon 2024 DRAM roadmap (via SemiEngineering, Tom's Hardware); Samsung IMW 2024 (via ZDNet Korea, Yole Group); Tokyo Electron 4F² VCT outlook (Tom's Hardware, April 2024); SK hynix VLSI 2024 3D DRAM test device (via TrendForce); SemiEngineering 3D DRAM cost threshold analysis; Samsung and SK hynix NAND layer announcements; TrendForce server DRAM bit supply outlook (July 9, 2026); Korea Cycle Data, "High-NA DRAM to 2033? Read the Dose Row First" and "3D DRAM Is Not 3D NAND". Everything here is from public sources.
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