High-NA DRAM to 2033? Read the Dose Row First
ASML's new High-NA EUV roadmap says 0.55NA can carry 2D DRAM through five more capacitor-pitch generations, out to 2033. Read the small print on the same slide and a different story appears: the dose needed to print the capacitor layer more than doubles between the 0A and 0C nodes, from 44 to 128 mJ/cm². Only two of the six nodes on the chart are process-qualified today. This post reads the slide row by row and checks whether the numbers hold together.
KEY TAKEAWAYS
1. The slide maps six DRAM nodes (1C to 0D) from capacitor pitch P34 to P22. Only 1C and 1D are process-qualified; 0A and 0B are in qualification; 0C and 0D are research items.
2. Dose falls to 44 mJ/cm² at 0A, then jumps to 104 at 0B and 128 at 0C while pitch barely moves. That is a stochastic-defect problem, not a resolution problem, and LCDU worsening from 1.2 to 1.73nm says the same thing.
3. The EXE:5200B is rated at 175 wafers per hour at 50 mJ/cm². A simple throughput model puts 128 mJ/cm² near 90 WPH. Beyond 0B, "High-NA lowers cost per bit" is a claim that has to be earned, not assumed.
What the slide actually says
The chart covers 2025 through 2033 and lists, for each node, the capacitor pitch, k1 factor, local CD uniformity (LCDU), depth of focus (DoF), dose and resist type. The values as I read them are below. The image resolution is limited, so a few cells (DoF at 0C, everything at 0D) are left blank rather than guessed.
| Node | Timing | Cap. pitch | k1 | LCDU (nm) | Dose (mJ/cm²) | Resist | Status |
|---|---|---|---|---|---|---|---|
| 1C | 2025-26 | P34 | 0.69 | 1.3 | 75 | CAR | Process qualified |
| 1D | 2027 | P30 | 0.61 | 1.2 | 66 | CAR | Process qualified |
| 0A | 2028-29 | P28 | 0.57 | 1.6 | 44 | CAR/MOR | Qualification ongoing |
| 0B | 2030 | P28-30 | 0.57-0.61 | 1.69 | 104 | CAR/MOR | Qualification ongoing |
| 0C | 2031-32 | P28-26 | 0.57-0.49 | 1.73 | 128 | MOR | Research |
| 0D | 2033 | P24-22 | 0.49-0.45 | - | - | MOR (simulation) | Research |
On the tool side, the public record is now fairly clear. SK hynix installed an EXE:5200B at a DRAM fab in September 2025, the first memory maker with a commercial High-NA system. Intel was reported in July 2026 as the first company to ship logic chips (18A, Panther Lake) with High-NA used on some layers. Imec took delivery of an EXE:5200 in March 2026 with a Q4 2026 qualification target. Cumulative High-NA wafer exposures were disclosed at 300,000 in January 2026 and 500,000 in March. A Korean research channel relays a newer ASML figure of ten tools running at four customers and 1.35 million wafers; I have not seen the primary source for that one.
One correction is worth making. The same channel quotes an "acceptance test" result of 135 WPH. ASML's published EXE:5200B specification is 175 WPH at 50 mJ/cm². The two numbers almost certainly describe different conditions and should not sit side by side without them. For reference, the productivity roadmap runs EXE:5200C at 190/160 WPH, 5200D at 195/175 and 5400E at 210/180 (without/with stitching), with the high-productivity EXE:5600 targeting 250 WPH or more.
Check 1: the k1 column reproduces the pitch column
Minimum printable half-pitch follows the Rayleigh relation CD = k1 × λ/NA. At 13.5nm and 0.55NA the λ/NA term is 24.5nm. Multiply the slide's k1 values by that and you get 16.9nm for 0.69 (P34), 15.0nm for 0.61 (P30), 14.0nm for 0.57 (P28) and 11.0nm for 0.45 (P22). Every row matches.
So the slide is really a plot of how far 0.55NA single exposure can be pushed along the k1 axis. For a contact-hole array, k1 around 0.45 is close to the practical single-exposure floor. 0D is the end of the High-NA line, and whatever comes after it is a different tool (Hyper-NA at 0.75) or a different device (3D DRAM). That is where the "five nodes" headline comes from, and it is a fair reading of the physics.
Check 2: the dose row is the real message
Dose moves the wrong way for the cost story. It improves from 75 at 1C to 44 mJ/cm² at 0A, then jumps to 104 at 0B and 128 at 0C. Pitch over that stretch barely changes, from P28 to a P28-26 range. If resolution were the constraint, dose and pitch would move together. They don't.
The next column explains why. LCDU, the local variation in hole size across a capacitor array, degrades from 1.2nm at 1D to 1.73nm at 0C. Variable hole size means variable cell capacitance and leakage, and at the tail it means missing or merged holes: stochastic defects. The blunt instrument for suppressing stochastics is more photons per hole, which is exactly what the dose row shows. Depth of focus shrinking from 70nm to the 40nm range narrows the process window at the same time, tightening wafer flatness, focus control and resist thickness requirements.
Check 3: what 128 mJ/cm² does to throughput
Take the EXE:5200B rating of 175 WPH at 50 mJ/cm². Model the time per wafer as a fixed overhead plus an exposure term proportional to dose, and assume exposure is 60% of the cycle at spec conditions. Under that model, 44 mJ/cm² gives 189 WPH, 75 gives 135, 104 gives 106 and 128 gives about 90.
The point is the direction, not the decimals. Halving throughput per scanner doubles the number of scanners needed for the same wafer output, and at roughly $400 million per tool that gap is a fab-scale capex line. The offset is source power: ASML has said its source runs at 1,000W under customer conditions with a path to 1,500W and beyond, and higher source power reclaims much of the dose penalty. The economics of High-NA DRAM beyond 0B come down to a race between dose creep and source power.
Two things the slide implies without saying
First, 0B's pitch (P28-30) is no tighter than 0A's P28. Advancing a node without shrinking the critical pitch means density is coming from somewhere else, most likely a cell layout or capacitor structure change. That is my inference, not something the slide states.
Second, the resist column moves from chemically amplified resist (CAR) to metal-oxide resist (MOR) across 0B and 0C, exactly where dose jumps. MOR absorbs EUV more efficiently and helps LCDU, but the supplier base is thin and the volume-production record is short. Resist supply becomes a named variable on the DRAM roadmap for the first time.
What I actually watch
| Checkpoint | What to look for | When |
|---|---|---|
| 0A qualification | ASML or a memory customer moving 0A to "process qualified" | 2027-28 |
| Source power | 1,000W to 1,500W timing and field deployment | Quarterly IR |
| MOR adoption | A memory fab confirming metal-oxide resist in volume | 2028 onward |
| High-NA shipments | Units recognized vs the 20-per-year target; memory share of the mix | ASML quarterly results |
Value chain read-through
| Segment | Direction | Why |
|---|---|---|
| Lithography tools | Positive | Higher dose means more scanners for the same output, at about $400M each |
| Etch and deposition | Neutral to negative | Fewer multi-patterning steps per wafer; a delayed 3D DRAM transition is the cushion |
| Resist and materials | Reshuffle | CAR to MOR opens the door for metal-oxide and dry-resist suppliers |
| DRAM makers | Gap widens | SK hynix and Samsung have High-NA; Chinese producers have no EUV access at all, and the gap compounds each generation |
Risks to this view
• The table is my reading of a slide image, not ASML's source file. Some cells may be misread.
• The throughput model is deliberately simple. Stitching, alignment and wafer-exchange time do not scale with dose and could change the shape of the curve.
• A roadmap is a tool vendor's plan. If customers stay on Low-NA multi-patterning past 0B, or move to 3D DRAM earlier, the table itself changes.
• The "ten tools, 1.35 million wafers" figure is second-hand. I will update when ASML's primary disclosure is available.
Bottom line
"Five more 2D DRAM nodes on High-NA" is true. The first two or three are the easy part. From 0B, three bills arrive together: dose, LCDU and resist. A roadmap slide shows what is possible; it is not a cost sheet. Keeping those two things apart is the whole point of this post.
Next: this roadmap laid alongside the 3D DRAM roadmap, to estimate how much runway 2D DRAM really has left.
Sources: ASML High-NA DRAM roadmap slide (September 2026, via Growth Research Telegram channel); Tom's Hardware, ASML lithography roadmap examined (May 1, 2026); More Than Moore, Intel starts shipping High-NA EUV silicon (July 17, 2026); TrendForce, imec secures EXE:5200 (March 19, 2026); Yahoo Finance/Zacks and Benzinga on cumulative High-NA wafers (January 16 and March 2, 2026); ASML EXE:5200B specification (175 WPH at 50 mJ/cm²). Everything here is from public sources.
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