Glass Substrate TGVs: Filled Copper vs Wall-Metallized Vias
A hole in glass is not yet a wire. Most glass-substrate coverage stops at how densely through-glass vias (TGVs) can be drilled, but the harder engineering question is what goes inside them. Dai Nippon Printing (DNP) now says it will make two kinds of TGV glass core: one with copper-filled vias and one with only the via walls metallized. The reason both exist comes down to a single material property.
KEY TAKEAWAYS
1. DNP plans 510 x 515 mm TGV glass cores in a "filled" and a "conformal" version. Its pilot line began phased operation in December 2025, with samples planned for early 2026 and a full mass-production structure targeted for fiscal 2028 (Dec 16, 2025 release).
2. Copper's coefficient of thermal expansion is 16.7 ppm/°C in a Corning patent, about 5x the 3.3 ppm/°C low end of the range AGC says it can tune packaging glass to (3.3 to 12.0).
3. That gap sets the trade-off. Filled vias give the lowest resistance but put the most stress on the glass. Conformal vias use far less copper but depend on getting metal to stick to a glass wall.
What DNP and TOPPAN actually disclosed
According to DNP's December 16, 2025 release, a new pilot line for TGV glass core substrates at its Kuki Plant in Saitama started phased operation that month. Sample shipments are planned for early 2026. DNP says it will "build the structure required for full mass production in FY 2028" while watching customer and market trends. DNP's fiscal year ends in March, so that window runs from April 2028 to March 2029. It is a plan, not a production date.
The release names both via types and says DNP wants to mass-produce high aspect ratio parts, meaning small via diameters relative to glass thickness. Its March 2023 release introduced the conformal type with an aspect ratio of 9 or more and a proprietary method to improve glass-to-metal adhesion, "which was difficult to achieve with conventional technology." The same 2023 release set a sales target of 5.0 billion yen for fiscal 2027.
TOPPAN's next-generation package page (undated, accessed October 5, 2026) shows glass substrates with TGVs plus cavities of different depths, meant to be combined with FC-BGA substrates. Its standard specs list glass 0.4 to 0.8 mm thick, via diameter/pitch from 60/130 µm to 80/150 µm, and cavity depth of 50 to 200 µm.
From hole to wire: three steps that inherit each other's defects
A June 2026 review in Micromachines (vol. 17, no. 6, article 720) breaks TGV metallization into via formation, adhesion and seed layer deposition, and copper plating, followed by polishing to remove excess copper and a thermal treatment. Each step inherits the previous one's flaws. Rough or micro-cracked via walls break the seed layer. A patchy seed layer distorts current during plating, which leaves voids and seams.
Via formation already involves a trade-off. Direct laser drilling is fast and flexible but has to manage taper, debris and microcracks. Laser modification followed by chemical etching gives cleaner walls but needs tight etch control. LPKF, which sells the second approach under the LIDE name, claims aspect ratios up to 1:50 and panel processing up to 600 x 600 mm on its technology page.
Filled vias: lowest resistance, highest stress
A copper-filled via is the best conductor and carries the most current. The first cost is plating. If the via mouth closes before the bottom fills, a void is trapped inside, so plating chemistry has to push growth from the bottom up. The review describes this bottom-up approach as effective but with a narrow process window.
The second cost is expansion. Corning patent US 11,760,682 B2 (granted September 2023) explains that heating a copper-filled glass part builds circumferential tensile stress in the glass, which forms radial cracks. Corning researchers have published on the same failure at ECTC 2021 and in Microelectronics Reliability (2021). As a rough illustration, take copper at 16.7 and glass at 3.3 ppm/°C and heat from room temperature to 250°C: the mismatch is about 0.3%, or about 1.2 µm over a 0.4 mm-deep via. That is my illustrative calculation, not a measured value.
Annealing cuts both ways. The review notes that heat treatment relaxes stress in plated copper but, if poorly tuned, can push copper up out of the via. That protrusion then disturbs the flat surface the next wiring layers need.
Conformal vias: less copper, harder adhesion
The same Corning patent lists the usual crack countermeasures: better CTE-matched glass, annular or conformally plated holes, anneals below roughly 300°C, and smaller holes. It adds that annular and small holes are not preferred for high-current uses. That is the conformal bargain in one sentence. You trade current capacity for lower stress. The center can be plugged, for example with resin, or left open; DNP has not said which it uses.
The catch is adhesion. Per the review, copper does not bond well to glass directly, so adhesion layers such as Ti, Cr or TiW are added, and sputtering, being line-of-sight, struggles to coat deep via walls evenly. Materials suppliers are targeting exactly this. MKS's Atotech unit markets VitroCoat GI, an ultra-thin metal-oxide adhesion promoter applied by dip coating, which it says covers high aspect ratio TGVs better than PVD. Its KPCA Show 2026 announcement (September 3) also listed a pulse plating chemistry for filling high aspect ratio TGVs.
Aspect ratio is glass thickness divided by via diameter. TOPPAN's 0.4 mm, 60 µm example works out to about 6.7. The same via through 0.8 mm of glass is 13.3. DNP argues that freedom in glass thickness helps with warpage and stiffness design, but a deeper via is also harder to seed all the way down.
Illustrative: how much copper a wall saves
Using a 60 µm via and calling the filled version 100, a conformal via with a 3 µm copper wall uses 19, a 5 µm wall uses 31 and a 10 µm wall uses 56. DC resistance scales inversely with cross-section, so those walls carry about 5.3x, 3.3x and 1.8x the resistance of the filled via. Illustrative calculation. Not actual company figures.
Cutting the copper slug to a third cuts the source of thermal stress, but carrying the same current then takes more vias or thicker walls. My reading is that this trade-off is why DNP offers both rather than picking one.
What I actually watch
| Checkpoint | Why it matters |
|---|---|
| DNP sample shipments | Confirms the early-2026 plan |
| DNP FY2027 sales target | 5.0bn yen set in 2023 |
| ECTC / IMAPS data | Crack and resistance shift by via type |
| Seed and adhesion adoption | Ti-free, electroless approaches |
| Published via specs | Diameter and pitch shrinking |
Value chain read-through
| Step | Public examples | What to track |
|---|---|---|
| Glass | AGC, Corning | CTE matching |
| Via formation | LPKF (LIDE) | Wall quality |
| Seed and plating | MKS Atotech | Coverage, voids |
| Substrate | DNP, TOPPAN | Samples to volume |
Risks to this view
• DNP and TOPPAN schedules and specs are company plans and development targets. Customers and adoption are not disclosed.
• CTE values are example figures from a patent and a research report. Actual product glass compositions are not public, so real stresses will differ.
• Chart 4 and the expansion-gap figure are illustrative calculations.
• Nothing here shows one via type winning. The choice depends on the application, such as RF or power delivery.
• This post does not estimate any toolmaker's orders or customer relationships.
In an earlier post on comparing glass substrate capacity claims, the focus was square meters. This one is about a single via. Intel said in September 2023 that glass could allow a 10x increase in interconnect density, and that promise depends on making each of those vias conduct reliably.
Sources: DNP releases (Dec 16, 2025; Mar 20, 2023); TOPPAN next-gen package substrate page (accessed Oct 5, 2026); Intel newsroom (Sep 18, 2023); Micromachines 17(6):720 TGV review (Jun 2026); Corning patents US 11,760,682 B2 and US 11,152,294 B2; Okoro et al., Microelectronics Reliability 120:114092 (2021) and ECTC 2021; AGC Research Report Vol. 67 (2017); LPKF LIDE technology page; MKS Atotech VitroCoat GI page and KPCA Show 2026 release (Sep 3, 2026).
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