Why Chip Fabs Ban Makeup: 3 Billion Particles in One Coat
Chip fabs ban makeup, and the reason is more specific than "keep it clean." A 1984 IBM study counted roughly 3 billion particles of 0.5 µm or larger from a single coat of mascara, and found 15 elements in common cosmetics, including sodium and potassium. One is a physical threat to wiring, the other an electrical threat to transistors.
KEY TAKEAWAYS
1. One mascara application released about 3 billion particles ≥0.5 µm; a full face, about 5.1 billion (Phillips et al., IES 1984). An ISO 3 cleanroom allows 35 such particles per cubic meter of air.
2. The industry roadmap treats a particle half the size of the circuit half pitch as a killer defect. By 2016, IRDS noted that killer size was already approaching 10 nm.
3. A single particle usually kills a single die. The expensive event is a contamination excursion: under illustrative assumptions, a yield drop from 91% to 64% across 20 lots is about $1.35 million.
Where the rule comes from
Intel's newsroom lists makeup alongside paper and pencils as items barred from its cleanrooms, all because they shed fine particles. The most cited evidence is older: a 1984 paper, "Cosmetics in Clean Rooms," presented at the Institute of Environmental Sciences by Phillips and colleagues at IBM's disk drive division in San Jose.
Cleanroom consultant Ken Goldstein later summarized that work in Semiconductor Digest and recommended a no-cosmetics rule for any room at ISO Class 7 or cleaner. The particle counts were striking: about 82 million particles from eye shadow, 3 billion from mascara, and 5.1 billion for a full application.
Path one: particles short or open the wiring
Metal lines on a wafer run in parallel at a fixed pitch. A particle that lands between two lines can bridge them into a short. A particle sitting on a line can mask the next deposition or etch step and leave an open. Either way, that die fails.
The roadmap gives a threshold. The ITRS 2007 Yield Enhancement chapter set the critical defect size at 50% of the half pitch; its 2007 MPU table pairs a 68 nm half pitch with a 34 nm critical defect. The IRDS 2016 yield chapter wrote that killer particle size, based on DRAM half pitch, had already approached 10 nm.
That reframes the 1984 numbers. The IBM team only counted particles of 500 nm and up, roughly 50 times today's killer size. Everything smaller went uncounted. As line widths shrink, a larger share of any given dust becomes lethal, which is why gowning and entry rules tighten with every node.
Path two: sodium moves the threshold voltage
Filters handle particles. Chemistry is harder. The IBM study identified 15 elements in cosmetics: sodium, magnesium, aluminum, silicon, phosphorus, sulfur, chlorine, bismuth, potassium, calcium, titanium, manganese, iron, barium and zinc.
Alkali metals such as sodium and potassium can enter the thin oxide under a transistor gate and drift as ions under an electric field. As they move, the voltage at which the transistor turns on shifts. Nothing is visibly broken, yet the chip no longer behaves as designed, which makes this the harder failure to trace.
This is one of the oldest problems in the industry. According to the Computer History Museum, Bruce Deal, Andrew Grove and Ed Snow at Fairchild identified sodium contamination as a cause of MOS instability between 1963 and 1966, and work at NEC, IBM and Philips resolved the yield and reliability issues by the end of the decade. A makeup ban is the cheapest way to keep that problem outside the door.
People are the largest source, and the garment decides by 10,000x
Even without makeup, people shed skin, hair and fiber. Philip Austin's Encyclopedia of Clean Rooms puts a slow walk at 5 million particles per minute in a snap smock, 500,000 in a standard coverall, 50,000 in a Tyvek coverall and 500 in a membrane coverall. Changing into a gown releases about 3 million per minute, which is why gowning happens outside the clean zone. The suit contains the body; the makeup rule covers the face the suit cannot.
One step further: is "one particle costs millions" true?
The ITRS chapter models random-defect yield with a negative binomial: Y = (1 + D0×A/α)^(−α), where D0 is defects per area, A is die area and α measures clustering.
Assume a 1 cm² die and α = 2. Yield is about 91% at 0.1 defects/cm², 76% at 0.3 and 64% at 0.5. Now assume each wafer carries $10,000 of sellable dies. A 27-point yield drop costs $2,700 per wafer and $67,500 per 25-wafer lot. If one contaminated tool touches 20 lots before it is caught, the bill is $1.35 million. A single particle costs one die; a single excursion is what gets expensive.
What I actually watch
| Signal | Why it matters |
|---|---|
| Cleanroom area in new fab announcements | Leads demand for filtration, HVAC and cleanroom build-out |
| Inspection and metrology spend | Defect density is yield; inspection scales with node shrinks |
| Process step count per node | More steps means more wafer cleans |
Value chain read-through
| Segment | What it controls | Driver |
|---|---|---|
| Cleanroom and HVAC | Airborne particles | New fab area |
| Inspection and metrology | Defect density | Node transitions |
| Wafer cleaning | Surface contamination | Step count |
| Cleanroom consumables | Particles from people | Fab headcount |
Risks to this view
• The 1984 counts reflect the cosmetics and instruments of that era. Modern products may differ.
• The yield and cost example is illustrative. Die area, clustering, wafer value and lot count are assumptions, not company figures.
• Cleanroom rules vary by company, area and class. The scope of any makeup ban follows each site's own policy.
If people are the biggest contamination source, why not take them out of the fab entirely? That is the next question: whether AI and automation will replace chip engineers, using public hiring and workforce data.
Sources: Intel Newsroom (2018-03-28); Samsung Semiconductor Newsroom (2012-04-12); Phillips et al., "Cosmetics in Clean Rooms" (IES, 1984), via K. Goldstein, Semiconductor Digest; P. Austin, Encyclopedia of Clean Rooms, Bio-Cleanrooms and Aseptic Areas (2000); ITRS 2007 Yield Enhancement; IRDS 2016 Yield; Computer History Museum, The Silicon Engine (1964 entry); ISO 14644-1:2015.
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