Why SK hynix Wants a Second Foundry for Its HBM Base Die
Herald Business reported exclusively on August 31 that SK hynix is weighing Intel Foundry, alongside TSMC, for the base die of its seventh-generation HBM4E. The base die was made in-house through HBM3E, moved to TSMC 12nm for HBM4, and was headed for TSMC 3nm in HBM4E. Adding Intel would make it the first dual-sourced base die among the three memory makers.
This post separates what the report establishes from what it implies, then looks at why the base die became the candidate for dual sourcing through three lenses: cost, supply chain, and packaging. It follows two earlier posts, on Samsung's 4nm base die roadmap and on SK hynix's HBM4 base-die requalification.
KEY TAKEAWAYS
1. Per the report, SK hynix is reviewing a multi-vendor setup that splits HBM4E base dies between TSMC and Intel Foundry. Combined with the Intel EMIB packaging tests it disclosed at Hot Chips, both the base die and the package would move from TSMC-only to a dual track.
2. The driver is cost. Industry estimates put the TSMC 12nm HBM4 base die at 3-4x the cost of a core die, which works out to 20-25% of die cost in a 12-high stack for a single chip. With HBM largely sold under long-term agreements, foundry cost increases are hard to pass through.
3. Intel's timing lines up. 18A is in production, EMIB-T rolls into fabs in 2026, 14A reaches volume in 2028. The only Intel node that fits a 2027 HBM4E window is the 18A family. The report does not name a node, and neither company has confirmed.
What the report says, and what it does not
Three things are established. SK hynix is, per industry sources, reviewing and pursuing a plan to use both TSMC and Intel for HBM4E base dies. The HBM4 base die is on TSMC 12nm and, per industry estimates, costs 3-4x a core die. And at Hot Chips 2026, Jaesik Lee, VP of package engineering at SK hynix America, said the company is comparing CoWoS-S, CoWoS-L and Intel EMIB. The last point has primary-source backing.
Three things are not established: which Intel node, what volume split, and which customer's parts. This is a single-source exclusive based on anonymous industry accounts, so this post treats it as a plan under review and will update if a disclosure or an Intel Foundry customer announcement confirms it.
Why the base die got expensive
The base die sits at the bottom of the stack, controls the 12 to 16 core dies above it, and connects to the GPU through a 2,048-bit interface. Through HBM3E it was built on a DRAM process. In HBM4 the pin count doubled from 1,024 to 2,048 and the PHY and controller grew complex enough to need a logic foundry node. TSMC's roadmap cuts operating voltage from 1.1V to 0.8V on its 12nm (12FFC) HBM4 base die, and for custom C-HBM4E on N3P it moves the memory controller itself onto the base die (TrendForce, Tom's Hardware, December 2025).
Apply the reported 3-4x to a 12-high stack: with twelve core dies at 12 units, one base die at 3-4 units is 20-25% of die cost. At 3nm the wafer cost rises again, so the share grows in HBM4E. This is a ratio-only illustration that leaves out packaging, yield and TSV costs.
Three suppliers, three answers
Samsung is producing HBM4 and HBM4E base dies in-house on Samsung Foundry 4nm and has said HBM5 moves to 2nm (Hot Chips 2026). Micron stayed on a DRAM process through HBM4 and moves to an advanced TSMC node for HBM4E, targeting 2027. SK hynix outsourced to TSMC 12nm from HBM4, was weighing TSMC 3nm for HBM4E, and per this report is now adding Intel.
That is what gives the report its meaning. Samsung controls cost and supply through vertical integration. Micron goes single-source to TSMC. SK hynix stays outsourced but splits the foundry to gain leverage. For a company without its own leading-edge logic fab, multi-vendor is the available cost response.
Why now, why Intel: three pressures
First, the TSMC bottleneck. UBS noted last November that TSMC N3 utilization could be tight into Q4 2026. If HBM4E base dies go to 3nm, they compete for wafers with the Nvidia and AMD GPUs they serve. A base die is a far smaller chip than a GPU, but one is needed per stack, so unit volume runs 8-12x the GPU count.
Second, the LTA structure. As the report notes, HBM is mostly sold under long-term agreements, so a foundry price increase cannot be pushed into the selling price mid-contract. In commodity DRAM, spot prices pull contracts upward; in HBM, the annual contract locks first. The remaining lever is cost.
Third, Intel's bundled pitch. Intel Foundry sells wafers and EMIB packaging under one roof. When reports surfaced on May 11 that SK hynix was testing EMIB for HBM integration, both stocks jumped, and Intel's CFO said in March that advanced packaging deals worth billions per year were close to closing (Tom's Hardware). DigiTimes reported in January that part of Nvidia's Feynman I/O die and up to 25% of its packaging could go to Intel, and TrendForce reported Google's plan to use EMIB in TPU v9 in 2027. A base die made at Intel sitting on Intel's EMIB is a natural pairing.
Which Intel node? Narrowing by timing
The report names no node, but timing narrows the field. Intel 14A reaches risk production in late 2027 and volume in 2028, per the CFO. The industry expects HBM4E volume in 2027 (TrendForce, January). The Intel nodes that can serve 2027 parts are the 18A family (18A, 18A-P) or something more mature. Intel itself puts the base die of Clearwater Forest on the mature Intel 3 node beneath 18A compute tiles, which is a useful reference point.
The choice matters because the base die's power and area characteristics differ by node, and the customer, whether Nvidia, AMD or an ASIC house, has to accept them. In the custom-HBM era the customer specifies the base die, so Intel volume is likely to be tied to specific customer programs. Customers adopting EMIB are the obvious candidates, but the report offers no evidence on this.
The cost of dual sourcing: requalification and design forks
Multi-vendor buys leverage but is not free. As covered in the earlier post, SK hynix's HBM4 base-die requalification affected Rubin supply timing. Changing the base die's foundry changes the PHY, the TSV interface and the thermal profile, which means a fresh customer qualification. Running a TSMC design and an Intel design in parallel doubles design and validation work.
Packaging dual sourcing is heavier still. As Lee explained at Hot Chips, the mechanical and thermal stress on an HBM cube differs across CoWoS-S, CoWoS-L and EMIB. "Base die made at Intel" and "stack mounted on EMIB" are two separate qualification events, not one.
What I actually watch
| When | What | Why |
|---|---|---|
| H2 2026 | Intel Foundry external customer announcements (14A, packaging commitments the CFO flagged) | Whether SK hynix is on the list, and on which node |
| Q4 2026 | SK hynix HBM4E customer qualification and 2027 contracts | Which customer the Intel-sourced base dies serve |
| H1 2027 | First EMIB-T accelerators in volume (Feynman I/O die, TPU v9) | Real demand for the base-die-plus-EMIB combination |
| Ongoing | TSMC N3 utilization and C-HBM4E customer announcements | Whether the TSMC bottleneck is the actual driver |
Value chain read-through
| Segment | Direction | Evidence |
|---|---|---|
| SK hynix | Leverage on base die cost, at the price of requal work | Reported plan; HBM4 requal precedent |
| Intel Foundry | Possible first base-die customer among the three memory makers; external validation of 18A | CFO on billions-per-year deals; EMIB test reports |
| TSMC | Small volume loss, but a signal | C-HBM4E roadmap assumes Micron and SK volume |
| Samsung | In-house strategy looks relatively stronger | 4nm base die in-house; 2nm plan for HBM5 |
| Substrates, packaging tools | EMIB-T substrate prepayments; four Taiwanese and two Japanese suppliers | Intel CEO at J.P. Morgan conference (TrendForce, May) |
Risks to this view
- Review-stage exclusive. No company confirmation; node, volume and customer undisclosed. A review may not become a contract.
- Intel 18A yield history. 18A had yield problems in 2025-26; reports say they were fixed, but there is no external high-volume track record yet. The base die is a single point of failure for the whole stack, so the yield bar is high.
- Requalification. The HBM4 base-die requal already disturbed supply timing once. Another foundry means more qualification events.
- The cost ratio's provenance. "3-4x" is an anonymous industry estimate, not a disclosed figure. The 20-25% share here is built on that ratio.
Bottom line
HBM's cost problem is migrating from the core die (DRAM) to the base die (logic). Samsung integrates, Micron single-sources to TSMC, SK hynix dual-sources: the three answers have diverged. If the review becomes a contract, Intel Foundry gets its first base-die customer among the memory makers and SK hynix gets a lever on a cost it cannot pass through. Intel's second-half customer announcements are the thing to watch.
Sources: Herald Business, "[Exclusive] SK hynix to Use Intel for Next-Gen HBM Base Dies," Aug 31, 2026 / TrendForce News (Mar 20, 2026 on SK hynix weighing TSMC 3nm, citing Chosun; Dec 1, 2025 on TSMC C-HBM4E N3P; Jan 23, 2026 on HBM4E timing; May 20, 2026 on EMIB substrate prepayments) / Tom's Hardware (May 11, 2026 on SK hynix EMIB tests and Intel CFO remarks; Dec 2, 2025 on TSMC and GUC base-die processes) / Wccftech, Apr 1, 2026 (Intel 14A schedule, packaging commitments) / Samsung and SK hynix at Hot Chips 2026, Aug 23, 2026 / Investing.com, Nov 20, 2025 (UBS on N3 utilization) / DigiTimes, Jan 27, 2026 (Nvidia Feynman and Intel, via BEP Research). Everything here is from public sources.
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