Why DRAM Is About to Be Built From Two Wafers
DRAM is about to stop being a single-wafer product. Samsung's ISSCC 2026 paper describes a 16 Gb DRAM built from two wafers — one carrying the memory cells, one carrying the peripheral logic — joined face-to-face by hybrid copper bonding. The industry shorthand for this stage is peri-stacking, or "2D POC": the cells are still a single planar layer, but the peripheral circuits have moved onto their own wafer. This post covers why the 4F² cell transition forces that split, what the bonding numbers look like, and which parts of the value chain move first.
KEY TAKEAWAYS
1. Moving the DRAM cell from today's 6F² layout to 4F² cuts cell area by roughly 30% and yields about 20% more chips per wafer — but it only pays off if the peripheral circuits leave the cell plane (POC/PUC architectures).
2. Samsung's ISSCC 2026 prototype bonds the cell and peri wafers with wafer-to-wafer hybrid copper bonding at a reported ~300nm pitch, after design work cut the required interconnects from 28.8 million to about 10 million.
3. Peri-stacking is the de-risking step before 3D DRAM. The bonding, inspection and design infrastructure being installed now gets reused when cell layers themselves start stacking — which is why equipment and metrology move earlier than the memory itself.
Why the peri has to move
A DRAM die carries two kinds of circuitry: the cell array that stores bits, and the peripheral circuits — sense amps, decoders, IO — that operate it. Since the 6F² cell layout arrived around 2007, both have shared the same silicon plane. Every square millimeter the peri occupies is a square millimeter the cell array doesn't get.
NAND solved this years ago by putting peripheral logic under or on a separate wafer from the array. DRAM couldn't follow: the capacitor module needs high-temperature steps that damage peripheral transistors built on the same wafer, among other constraints. So the peri stayed beside the cells — until the 4F² transition made the split unavoidable.
Vendors use several names depending on which way the stack is described — peri-over-cell (POC), peri-under-cell (PUC), cell-over-peri (COP). The mechanics are the same: build the cell array and the peripheral logic on separate wafers, each on its own optimized process, then bond them. Because the cell array itself is still one planar layer, this stage is often called "2D POC" to distinguish it from true 3D DRAM, where the cells stack.
What 4F² buys, and what it costs
4F² is the theoretical floor for a one-transistor, one-capacitor cell footprint. Getting there requires standing the access transistor vertically (Samsung calls its version VCT, vertical channel transistor; SK hynix presented a vertical gate, VG, platform) with the bitline buried underneath. Per Samsung's ISSCC 2026 presentation as reported by THE ELEC, cell area shrinks about 30% versus 6F² and chip output per wafer rises roughly 20%.
The cost is process complexity. A vertical transistor with a capacitor stacked above it and a buried bitline below is a different manufacturing problem from today's planar flow. Splitting the product across two wafers turns one very hard process into two manageable ones: the cell wafer runs a cell-optimized flow, the peri wafer runs a logic-optimized flow, and neither compromises for the other. The extra cell area freed by evicting the peri is the bonus on top.
The bonding numbers
The two wafers meet through wafer-to-wafer hybrid copper bonding — copper pads and dielectric joined directly, no bumps. Samsung's reported bond pitch is around 300nm. For scale, the microbumps inside an HBM stack sit tens of micrometers apart; this is two orders of magnitude denser.
Interconnect count is a design lever, not a given. THE ELEC reports Samsung cut the wafer-to-wafer connections from 28.8 million to about 10 million through design optimization — fewer joints means less overlay risk and less yield exposure. The remaining hard problems are bonding alignment and void inspection at the bond interface, which is why non-destructive inspection tools for hybrid bonding are reportedly being qualified on production lines.
The stepping stone to 3D DRAM
All three vendors frame peri-stacking as a waypoint, not a destination. SK hynix's VLSI 2025 keynote laid out a 30-year roadmap running from 4F² VG with PUC through to 3D DRAM. Samsung followed its ISSCC prototype with media reports pointing to production adoption around 2028. Micron, per trade press, may skip 4F² and go straight to 3D DRAM. And analysis from SemiAnalysis credits CXMT with adopting a 4F²/vertical-transistor layout early — worth noting because structural scaling reduces dependence on the most advanced lithography, which is exactly where Chinese vendors are constrained.
The sequencing logic is straightforward: stacking cell layers is the hardest step, so vendors first de-risk everything around it. Keep the cells planar, move only the peri, and use that generation to qualify wafer bonding, bond-interface inspection and the two-wafer design methodology. When 3D DRAM arrives in the 2030s, the bonding infrastructure is already paid for and yielding.
What I actually watch
| Checkpoint | Why it matters |
|---|---|
| IEDM (Dec) and next VLSI papers | Whether 4F²/3D DRAM follow-ups show yield and reliability data, not just architecture |
| Official node assignment for 4F² | The moment a vendor names the production node, equipment orders get a date |
| Bonder and inspection tool orders | HBM hybrid bonding and DRAM W2W bonding share an ecosystem — watch which label the orders carry |
Value chain read-through
| Segment | Exposure | Signal to track |
|---|---|---|
| Bonding equipment | New W2W hybrid bonding demand per DRAM wafer pair | Order disclosures, joint conference papers |
| Inspection / metrology | Bond-interface void detection is a new mandatory step | Production-line qualification reports |
| Materials | Bonding dielectrics and CMP slurry volumes rise | Qualification wins at memory makers |
| Memory vendors | Transition timing and node choice drive cost curves | 4F²/3D DRAM language in IR materials |
Risks to this view
• This is a prototype disclosure. Production yield and cost qualification are separate gates, and neither has been demonstrated publicly.
• Two wafers plus a bonding step means cost per bit likely rises before it falls. Early 4F² generations may be premium-only.
• The ~2028 production timing comes from media reporting, not company guidance. It can slip.
• If a direct-to-3D path matures faster than expected, the peri-stacking generation could be shorter-lived than the infrastructure spend assumes.
DRAM is following the road NAND already walked — peripheral logic off the cell plane — but with wafer bonding as the vehicle instead of monolithic integration. Next up in this series: what actually changes when the cells themselves lie down and stack, and why 3D DRAM is a different beast from 3D NAND.
Sources: Samsung ISSCC 2026 disclosure as reported by THE ELEC; SK hynix newsroom and VLSI 2025 keynote; SK hynix 4F² VG/PUC paper (IEEE); THE ELEC and Seoul Economic Daily reporting; SemiAnalysis. All accessed August 2026.
Disclaimer: This post is for informational and educational purposes only. It does not constitute investment advice or a recommendation to buy or sell any security. All investment decisions are your own responsibility.
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