Three Companies Can Now Build HBM4. That Changes Everything.
Three companies can now build HBM4. That single fact has changed what matters in the memory market, and most coverage has not caught up to it yet.
Below is where the competition actually stands as of Q2 2026, why stacking DRAM is harder than it sounds, and the specific numbers I watch instead of the headlines.
KEY TAKEAWAYS
1. HBM4 did not get faster. It got wider — I/O count doubled from 1,024 to 2,048.
2. The share table flipped. Q2 2026 DRAM: Samsung 39%, SK hynix 26%, Micron 25%. A year earlier SK hynix held 39%.
3. The contest is no longer about who can build it. It is about who can ship it, at yield, in volume.
1. Where the race actually stands
Announcements versus shipments
HBM4 moved out of the qualification phase during the first half of 2026.
- Samsung announced the industry's first HBM4 mass-production shipment on February 12, 2026, built on its 1c-nm DRAM process.
- SK hynix had earlier announced, in September 2025, that HBM4 development was complete and a production system was in place — using 1b-nm DRAM and its advanced MR-MUF packaging.
- By late July 2026, Micron had passed one billion dollars in HBM4 revenue, while SK hynix reported bringing HBM4 yield and quality up to HBM3E levels ahead of a second-half ramp.
A note on "world's first." Each company defines the milestone differently. Development complete, sample shipment, production-transition approval, and actual volume shipment are four separate events that press coverage tends to collapse into one. For investment purposes, only two of them matter: units shipped and customer qualification passed.
According to Counterpoint Research, Samsung took the DRAM lead in Q2 2026 with 39% share — a notable turnaround given it had ceded the top spot to SK hynix a year earlier. SK hynix fell from 39% to 26% despite growing revenue 214% year over year. Micron reached 25%, having multiplied its DRAM revenue roughly fivefold, and now sits within a point of second place.
The interpretation matters more than the numbers. Falling share does not mean falling volume here. The total addressable market is expanding fast enough that all three suppliers are growing. Much of Samsung's move is a normalization from an unusually depressed 2025 base rather than share taken from anyone. SK hynix growing 214% while losing 13 points of share is the clearest evidence of that dynamic.
2. Why stacking DRAM is hard
Three difficulty points, and where each one bites
A GPU sitting idle while it waits for data is the memory-bandwidth problem in one sentence. Conventional DRAM addresses it by making a narrow road faster. HBM does the opposite: it widens the road.
HBM4 doubled the I/O count from 1,024 to 2,048 relative to HBM3E, delivering roughly twice the bandwidth with meaningfully better power efficiency. In a datacenter, that efficiency figure is not a spec-sheet nicety — it is the electricity bill, and it is the ceiling on how densely you can pack racks.
An HBM package is built from core dies — stacked DRAM — sitting on top of a base die that handles logic. The manufacturing difficulty concentrates in three places.
Through-Silicon Vias
Thousands of microscopic holes are drilled through each die and filled with copper to connect layers vertically. Alignment error accumulates with every layer added. At 12-high and 16-high, a single misaligned die can scrap the entire package.
Stacking and packaging
The two Korean suppliers made opposite bets here. SK hynix applied its established advanced MR-MUF process together with 1b-nm DRAM, explicitly to minimize ramp risk. Samsung went to the newer 1c-nm node, trading process maturity for performance headroom. Stability versus performance — that choice is the strategic fault line in this generation.
The base-die handoff
This is the structural change that gets underweighted. With HBM4 requiring customer-specific functionality and tighter yield control, SK hynix moved base-die production to TSMC's advanced logic process rather than building it in-house.
The implication is that a memory company now depends on a foundry partner for part of its own product. Samsung counters with a turnkey position — memory, foundry, and packaging under one roof. SK hynix answers with the TSMC alliance. Bargaining power in the value chain is shifting, and it is worth watching which model the large AI customers actually prefer over the next few quarters.
3. The math of yield
Why HBM is expensive, in one calculation
HBM commands its price because defects multiply rather than add.
Take a 12-high stack where each layer is 95% good. The compound yield is 0.9512, or roughly 54%. Every individual process step looks excellent, and nearly half the finished packages still get scrapped.
Three consequences follow:
- The cost of every scrapped package is carried by the units that ship.
- A few percentage points of yield improvement translate almost directly into operating margin.
- For the same wafer starts, weak yield reduces shippable volume itself — which is why capacity and yield cannot be analyzed separately.
This is the reason SK hynix stating that HBM4 yield had reached HBM3E levels was treated as material news. It was a volume statement, not a quality statement.
4. The generation shift is slower than the headlines
Research and brokerage estimates put HBM3E at roughly two-thirds of 2026 HBM shipments, with HBM4 building its share gradually through the year.
Nearly all the coverage is about HBM4. Most of this year's revenue still comes from HBM3E. There is always a lag between a product announcement and its contribution to the income statement, and in memory that lag runs two to four quarters.
5. What I actually watch
| Indicator | Why it matters |
|---|---|
| HBM revenue mix on earnings calls | More precise than share headlines. Guidance on shipment volume is the real signal. |
| Packaging capacity build-out | HBM consumes roughly three times the wafer area of standard DRAM. Back-end line timing is supply capability. |
| Customer roadmap sync | Next-generation accelerator launch timing is effectively the only demand trigger. If it slips, memory earnings slip with it. |
| Contract price direction | Some forecasters expect HBM pricing to correct as three-supplier competition and added capacity arrive. |
Value chain read-through
| Back-end equipment & materials | More TSV, stacking and bonding steps per unit |
| Test equipment | Higher stack counts mean more inspection stages |
| Foundry | Base-die outsourcing creates a new demand stream |
| Power & cooling infrastructure | The datacenter bottleneck is already migrating away from memory |
That last row is the one I would flag. Watch memory cycles long enough and a pattern emerges: the bottleneck always moves. If HBM is the constraint today, power and thermal capacity are the constraint being built toward next.
Risks to this view
- HBM price premium compressing as the three-supplier structure completes
- Demand deferral if customer accelerator roadmaps slip
- Chinese memory capacity expansion pressuring commodity DRAM pricing
- Structural fragility from heavy concentration in a small number of end customers
To summarize: HBM has passed out of a technology race and into a supply race. Now that all three suppliers can build the part, the numbers worth tracking are yield, packaging capacity, and units actually shipped — not press releases.
Next post: reading the current position of the memory cycle through Korean customs export data, which publishes on a monthly cadence and tends to lead reported earnings.
Sources: Counterpoint Research, Samsung Electronics Newsroom, SK hynix Newsroom, company earnings disclosures.
Disclaimer: This post is for informational and educational purposes only. It does not constitute investment advice or a recommendation to buy or sell any security. All investment decisions are your own responsibility.
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