Rubin's 22 TB/s HBM4 Number the JEDEC Spec Can't Explain
Nvidia's generation-over-generation GPU launches get read as a compute story. The number that has actually moved the most since 2016 is memory. Per-GPU HBM bandwidth is up roughly 30 times, from 0.72 TB/s on the Pascal-era P100 to a targeted 22 TB/s on Rubin, the platform Nvidia moved into production at CES 2026.
That climb is also where this year's real supply-chain story sits. The JEDEC HBM4 standard alone cannot produce Rubin's headline bandwidth number, and as of this month the memory makers building it are already having to walk that number back. Below is what the public record — Nvidia's own materials, the JEDEC spec, trade press, and Korean disclosures — actually supports.
KEY TAKEAWAYS
1. Nvidia's per-GPU HBM bandwidth rose about 30x in a decade — 0.72 TB/s (P100, 2016) to a targeted 22 TB/s (Rubin, 2026) — while capacity grew 18x, from 16GB to 288GB.
2. Rubin's 22 TB/s spec implies roughly 10.7 Gbps per pin, about 34% above the JEDEC HBM4 standard's 8 Gbps baseline. As of August 2026, multiple reports say Nvidia has already trimmed the shipping target toward roughly 20 TB/s because memory suppliers could not hold the higher speed at volume.
3. Counterpoint Research's Q1 2026 tracker shows SK hynix holds 58% of the HBM market but just 29% of overall DRAM share — a reminder that "Korean memory maker" and "HBM exposure" are not interchangeable bets (Samsung: 38% DRAM / 21% HBM; Micron: 22% DRAM / 21% HBM).
Six generations, one number that actually moved
Line up Nvidia's data-center GPUs since 2016 and the compute figures tell a familiar story of steady, expected gains. Memory bandwidth tells a different one. It roughly doubled from P100 (2016) to A100 (2020), then compounded faster: H100 hit 3.35 TB/s in 2022, H200 reached 4.8 TB/s in 2024, and Blackwell-generation parts (B200, then GB300) pushed to 8 TB/s. Rubin's announced target of 22 TB/s is nearly triple the prior generation's figure in a single step.
Put another way: it took six years (2016–2022) for bandwidth to go up roughly 4.7x. It took four more years (2022–2026) for it to go up another 6.6x on top of that. The pace is accelerating, not leveling off, which is unusual for a component category that used to move on a slower, more predictable cadence.
Capacity kept pace, just not as fast
Memory capacity grew alongside bandwidth but at a gentler rate: 16GB (P100) to 288GB (Rubin) is an 18x increase over the same stretch, versus roughly 30x for bandwidth. That gap matters. Nvidia has been optimizing harder for how fast data moves off the chip than for how much of it a single GPU can hold, which tracks with where the bottleneck actually sits in large-model training and inference — feeding the compute units, not storing more parameters on one package.
Nvidia's own roadmap points to Rubin Ultra in the second half of 2027, with HBM4E capacity announced at 1TB per GPU. I would not treat that figure as locked in. Reporting from mid-August 2026 — after the Korean-language source for this piece was drafted — indicates Nvidia is testing lower-memory Rubin Ultra configurations, including capacities as low as 192–256GB and a possible step back from HBM4E to plain HBM4, because HBM supply has not kept up with the roadmap. That would put Rubin Ultra below Rubin's own 288GB in some configurations, which is a genuinely unusual direction for a "next-gen" part to move in.
Per-GPU HBM capacity by generation. The Rubin Ultra bar is an announced roadmap target, not a shipping spec.The 22 TB/s number the JEDEC spec can't explain
JEDEC finalized the HBM4 standard (JESD270-4) on April 16, 2025. It doubles the interface width to 2,048 bits per stack, doubles independent channels to 32, and sets a baseline per-pin speed of up to 8 Gbps — for a maximum of about 2 TB/s per stack under the standard alone.
Rubin's published spec is 288GB across 8 stacks at 22 TB/s. Divide that out: 2,750 GB/s per stack, which at a 2,048-bit interface works out to roughly 10.7 Gbps per pin — about 34% faster than the JEDEC baseline. That is not a standard-compliant number; it is a customer-specific requirement layered on top of the standard.
The gap is not theoretical. According to EE Times' coverage of CES 2026, Nvidia raised its required HBM4 pin speed to above 11 Gbps in the third quarter of 2025, which sent all three memory suppliers back to resubmit samples. Meeting the JEDEC spec and meeting Nvidia's actual purchase requirement are two different qualification processes — commodity DRAM sells once it meets a published standard, but HBM is re-validated every time a customer's target spec moves.
That process is still unsettled. Press reports from August 2026 put Nvidia's revised, shippable bandwidth target closer to 20 TB/s — roughly 10 Gbps per pin — after SK hynix and Samsung were unable to hold the higher speed at production volume. I'd treat 22 TB/s as the announced target rather than the number that ships in volume; see Risks for detail.
One Rubin system, three different memory jobs
A second structural shift is easy to miss if you only track the headline HBM number. Starting with Rubin, a single Nvidia AI system draws on three distinct memory types instead of one: HBM4 next to the GPU for maximum bandwidth, LPDDR5X-based SOCAMM2 modules next to the Vera CPU for capacity and power efficiency, and GDDR7 in the inference-focused Rubin CPX for cost efficiency on long-context workloads.
SK hynix announced mass production of a 192GB SOCAMM2 module on April 20, 2026, built on its sixth-generation (1c) 10-nanometer-class LPDDR5X process. The company's own materials claim more than double the bandwidth of a conventional RDIMM and more than 75% better power efficiency. Rubin CPX, unveiled September 9, 2025, uses 128GB of GDDR7 — memory that's cheaper and runs cooler than HBM, aimed specifically at long-context inference rather than training.
There is a second, quieter shift bundled into this: the HBM4 base logic die is moving from a memory maker's own process to a foundry's logic process. According to EE Times' CES 2026 reporting, SK hynix's base die runs on TSMC's 12-nanometer node while Samsung uses its own 4-nanometer foundry process. TrendForce reported in March 2026 that SK hynix was evaluating TSMC's 3-nanometer node for HBM4E, though that is not yet confirmed. Structurally, this puts a foundry line item into a DRAM maker's cost structure for the first time and opens the door to genuinely customized HBM designed around a specific customer's logic.
TrendForce's June 2026 outlook adds a capacity-planning wrinkle worth flagging here: it estimates the three suppliers' combined 2027 LPDRAM output will only cover about 60% of Nvidia's projected LPDRAM demand, and that AI servers won't overtake smartphones as the largest LPDRAM demand source until sometime in 2028–2030. Nvidia's own response, per TrendForce, has reportedly been to shrink per-module capacity and increase module count rather than accept a lower total — a supply-allocation workaround, not a change in total demand.
Same company, very different HBM exposure
This is the part of the story that is easiest to get wrong from outside Korea, and it's where customs and disclosure data available here add real value. Counterpoint Research's Q1 2026 tracker puts overall DRAM market share at Samsung 38%, SK hynix 29%, and Micron 22%. Narrow that to HBM alone and the ranking flips: SK hynix 58%, Samsung 21%, Micron 21%.
The practical implication: "exposure to the memory cycle" and "exposure to the HBM cycle" are not the same trade. SK hynix carries roughly double the HBM concentration of its overall DRAM share, meaning its results move disproportionately with AI accelerator demand. Samsung's overall DRAM lead is real, but a much smaller share of that business is currently HBM — its results are more tied to general-purpose DRAM and NAND pricing than to Nvidia's roadmap specifically. This is a live, quarter-to-quarter number, and I'd expect the specific percentages to shift as Rubin ramps.
What I actually watch
| Checkpoint | What to watch for |
|---|---|
| Rubin shipment volume vs. total HBM demand | These are separate questions. TrendForce has already cut Rubin's 2026 share of HBM shipments (29% → 22%) while raising Blackwell/HBM3E's share (61% → 71%). A Rubin delay does not automatically mean weaker total HBM demand — it can mean a longer Blackwell tail instead. |
| Stack height and pin speed at each supplier's next mass-production announcement | Per EE Times, SK hynix is targeting 16-layer, 48GB HBM4 for Q3 2026; Micron has submitted final samples at 12-layer, 36GB. Layer count and pin speed together determine both yield economics and whether a given supplier clears Nvidia's actual bar, not just the JEDEC minimum. |
| Base-die foundry node selection | SK hynix (TSMC 12nm today, reportedly evaluating TSMC 3nm for HBM4E) versus Samsung's in-house 4nm decision will shape both power/cost profiles and how "custom" each company's HBM offering can get for a given customer. |
| LPDDR5X / SOCAMM2 capacity additions | Per TrendForce, the three suppliers' 2027 output only covers about 60% of Nvidia's projected demand. Watch whether Nvidia's module-count workaround holds, or whether this becomes a second bottleneck alongside HBM. |
Value chain read-through
| Segment | Confirmation indicator | Read-through |
|---|---|---|
| GPU-side HBM4/HBM4E (SK hynix, Samsung, Micron) | Mass-production timing, stack height, achieved pin speed | Highest direct leverage to Rubin's ramp; SK hynix's HBM concentration (58% share) makes it the purest read on this specific cycle. |
| Base-die logic (foundries) | Node selection, custom-HBM order flow | New revenue line for foundries from a category (memory) they didn't previously touch; watch for disclosed HBM-related capacity commitments. |
| CPU-side LPDDR5X/SOCAMM2 | Module capacity, LPDDR production capacity additions | A second, less-watched AI memory demand stream; TrendForce's supply-gap estimate suggests this could tighten before HBM does. |
| Inference-only GDDR7 (Rubin CPX) | Actual Rubin CPX shipment volume | Smaller, cheaper memory pool; matters more to inference-cost economics than to the headline HBM story. |
| Back-end packaging (TSV, MR-MUF, hybrid bonding) | Timing of the industry's shift to 16-layer stacks | Packaging technique choice affects yield and cost at high layer counts; a natural next-post topic. |
Risks to this view
- The headline 22 TB/s figure may already be stale. Multiple August 2026 reports indicate Nvidia has lowered its shipping bandwidth target for Rubin toward roughly 20 TB/s after SK hynix and Samsung could not sustain the required pin speed at volume. This is recent, still-developing reporting rather than a confirmed Nvidia specification change, and I would not be surprised to see the number move again before Rubin actually ships at scale in the second half of 2026.
- Rubin Ultra's roadmap is unusually unsettled for a part still over a year from launch. Reports of Nvidia testing 192–256GB configurations, and a possible step back from HBM4E to HBM4, would represent a real reduction in ambition versus the originally announced 1TB. Roadmap figures this far out are routinely revised and should be treated as directional, not committed.
- TrendForce, Counterpoint, and EE Times figures cited here are third-party research and trade-press reporting, not audited company disclosures. Shipment-share and pin-speed estimates in particular can shift meaningfully between report vintages; treat the specific percentages as a snapshot of Q1 2026 conditions, not a fixed ranking.
- Base-die foundry node decisions (e.g., SK hynix's reported evaluation of TSMC's 3nm process) are unconfirmed as of this writing. A different node choice would change the cost and power picture materially.
- Korea's July 2026 semiconductor export growth (+178.8% year-on-year) sits on an already-elevated 2025 base. A slowdown in that growth rate in coming months would reflect base effects working against the comparison, not necessarily a weakening cycle — the two are easy to conflate in headline coverage.
The bandwidth and capacity numbers Nvidia announces at its own events are a starting point, not the final word — this post exists because the gap between the announced spec and what actually ships is where the more interesting, Korea-specific story sits: which supplier's stack height and pin speed clear the bar first, and how exposed each company's earnings actually are to that outcome versus to memory pricing in general. Next up, I plan to dig into the back-end packaging question flagged in the value-chain table above — specifically, the timing of the industry's shift to 16-layer HBM stacks and what that does to yield economics at each supplier.
Sources: Nvidia newsroom materials (Jan 5, 2026; May 31, 2026; Sep 9, 2025); JEDEC JESD270-4 (Apr 16, 2025); EE Times, "The State of HBM4 Chronicled at CES 2026"; TrendForce (Mar/Apr/Jun 2026); Counterpoint Research (Q1 2026 DRAM/HBM tracker); SK hynix SOCAMM2 mass-production announcement (Apr 20, 2026); Korea Ministry of Trade, Industry and Energy, July 2026 trade statistics; TechPowerUp and Tom's Hardware reporting on Rubin/Rubin Ultra spec revisions (Aug 2026).
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